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| this is information on a product in full production. february 2017 docid027114 rev 3 1/83 STM32F070CB stm32f070rb stm32f070c6 stm32f070f6 arm ? -based 32-bit mcu, up to 128 kb flash, usb fs 2.0, 11 timers, adc, communication interfaces, 2.4 - 3.6 v datasheet - production data features ? core: arm ? 32-bit cortex ? -m0 cpu, frequency up to 48 mhz ? memories ? 32 to 128 kbytes of flash memory ? 6 to 16 kbytes of sram with hw parity ? crc calculation unit ? reset and power management ? digital & i/os supply: v dd = 2.4 v to 3.6 v ? analog supply: v dda = v dd to 3.6 v ? power-on/power down reset (por/pdr) ? low power modes: sleep, stop, standby ? clock management ? 4 to 32 mhz crystal oscillator ? 32 khz oscillator for rtc with calibration ? internal 8 mhz rc with x6 pll option ? internal 40 khz rc oscillator ? up to 51 fast i/os ? all mappable on external interrupt vectors ? up to 51 i/os with 5v tolerant capability ? 5-channel dma controller ? one 12-bit, 1.0 s adc (up to 16 channels) ? conversion range: 0 to 3.6 v ? separate analog supply: 2.4 v to 3.6 v ? calendar rtc with alarm and periodic wakeup from stop/standby ? 11 timers ? one 16-bit advanced-control timer for six-channel pwm output ? up to seven 16-bit timers, with up to four ic/oc, ocn, usable for ir control decoding ? independent and system watchdog timers ? systick timer ? communication interfaces ? up to two i 2 c interfaces ? fast mode plus (1 mbit/s) support, with 20 ma current sink ? smbus/pmbus support (on single i/f) ? up to four usarts supporting master synchronous spi and modem control; one with auto baud rate detection ? up to two spis (18 mbit/s) with 4 to 16 programmable bit frames ? usb 2.0 full-speed interface with bcd and lpm support ? serial wire debug (swd) ? all packages ecopack ? 2 lqfp64 10x10 mm lqfp48 7x7 mm tssop20 www.st.com
contents STM32F070CB/rb/c6/f6 2/83 docid027114 rev 3 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 arm ? -cortex ? -m0 core with embedded flash and sram . . . . . . . . . . . 12 3.2 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 cyclic redundancy check calculation unit (crc) . . . . . . . . . . . . . . . . . . . 13 3.5 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.2 power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7 general-purpose inputs/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.8 direct memory access controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9 interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9.1 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 16 3.9.2 extended interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . 16 3.10 analog to digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.1 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.2 internal voltage reference (v refint ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.11 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11.1 advanced-control timer (tim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11.2 general-purpose timers (tim3, tim14..17) . . . . . . . . . . . . . . . . . . . . . . 19 3.11.3 basic timers tim6 and tim7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11.4 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11.5 system window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11.6 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12 real-time clock (rtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.13 inter-integrated circuit interfaces (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14 universal synchronous/asynchronous receiver/transmitter (usart) . . . 21 docid027114 rev 3 3/83 STM32F070CB/rb/c6/f6 contents 4 3.15 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16 universal serial bus (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17 serial wire debug port (sw-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.3.2 operating conditions at power-up / powe r-down . . . . . . . . . . . . . . . . . . 40 6.3.3 embedded reset and power control bloc k characteristics . . . . . . . . . . . 40 6.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.3.6 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.3.7 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.3.8 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.3.9 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3.10 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.3.12 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3.13 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3.14 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3.15 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.16 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.3.17 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.18 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 contents STM32F070CB/rb/c6/f6 4/83 docid027114 rev 3 6.3.19 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.1 lqfp64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.2 lqfp48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.3 tssop20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.4.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 docid027114 rev 3 5/83 STM32F070CB/rb/c6/f6 list of tables 6 list of tables table 1. STM32F070CB/rb/c6/f6 family device features and peripheral counts . . . . . . . . . . . . . . 10 table 2. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 3. internal voltage reference calibrati on values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6. STM32F070CB/rb/c6/f6 i 2 c implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. stm32f70x0 usart implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8. STM32F070CB/rb/c6/f6 spi implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 9. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 10. stm32f070xb/6 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 11. alternate functions selected through gpioa_af r registers for port a . . . . . . . . . . . . . . . 30 table 12. alternate functions selected through gpiob_af r registers for port b . . . . . . . . . . . . . . . 31 table 13. alternate functions selected through gpioc_af r registers for port c . . . . . . . . . . . . . . . 32 table 14. alternate functions selected through gpiod_af r registers for port d . . . . . . . . . . . . . . . 32 table 15. alternate functions selected through gpiof_afr registers for port f. . . . . . . . . . . . . . . . 32 table 16. STM32F070CB/rb/c6/f6 peripheral register bound ary addresses. . . . . . . . . . . . . . . . . . 34 table 17. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 18. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 19. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 20. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 21. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 22. embedded reset and power control block characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 23. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 table 24. typical and maximum current consumption from v dd supply at v dd = 3.6 v . . . . . . . . . . 42 table 25. typical and maximum current consumption from the v dda supply . . . . . . . . . . . . . . . . . . 42 table 26. typical and maximum consumption in stop and standby modes . . . . . . . . . . . . . . . . . . . 43 table 27. typical current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 28. switching output i/o current cons umption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 29. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 30. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 31. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 32. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 33. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 34. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 35. hsi14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 36. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 37. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 38. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 39. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 40. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 41. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 42. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 43. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 44. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 45. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 46. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 47. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 list of tables STM32F070CB/rb/c6/f6 6/83 docid027114 rev 3 table 48. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 49. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 50. r ain max for f adc = 14 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 51. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 52. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 53. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 54. iwdg min/max timeout period at 40 khz (lsi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 55. wwdg min/max timeout value at 48 mhz (pclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 56. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 57. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 58. usb electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 59. lqfp64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 60. lqfp48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 61. tssop20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 62. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 63. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 64. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 docid027114 rev 3 7/83 STM32F070CB/rb/c6/f6 list of figures 7 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3. lqfp64 64-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 4. lqfp48 48-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5. tssop20 20-pin package pinout (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 6. STM32F070CB/rb/c6/f6 memory ma p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 7. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 8. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 9. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 10. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 11. high-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 12. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 13. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 14. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 15. tc and tta i/o input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 16. five volt tolerant (ft and ftf) i/o input characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 17. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 18. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 19. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 20. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 21. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 22. spi timing diagram - slave mode and cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 23. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 24. lqfp64 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 25. lqfp64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 26. lqfp64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 27. lqfp48 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 28. lqfp48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 29. lqfp48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 30. tssop20 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 31. tssop20 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 32. tssop20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 introduction STM32F070CB/rb/c6/f6 8/83 docid027114 rev 3 1 introduction this datasheet provides the ordering informat ion and mechanical devic e characteristics of the STM32F070CB/rb/c6/f6 microcontrollers. this document should be read in conjun ction with the stm32f0x0xx reference manual (rm0360). the reference manual is available from the stmicroelectronics website www.st.com . for information on the arm ? cortex ? -m0 core, please refer to the cortex ? -m0 technical reference manual, available from the www.arm.com website. docid027114 rev 3 9/83 STM32F070CB/rb/c6/f6 description 23 2 description the STM32F070CB/rb/c6/f6 microcontrollers incorporate the high-performance arm ? cortex ? -m0 32-bit risc core operating at a 48 mhz frequency, high-speed embedded memories (up to 128 kbytes of flash memory and up to 16 kbytes of sram), and an extensive range of enhanced peripherals and i/os. all devices offer standard communication interfaces (up to two i 2 cs, up to two spis and up to four usarts), one usb full speed device, one 12-bit adc, seven general-purpose 16-bit timers and an advanced- control pwm timer. the STM32F070CB/rb/c6/f6 microcontrollers op erate in the -40 to +85 c temperature range from a 2.4 to 3.6v power supply. a comprehensive set of power-saving modes allows the design of low-power applications. the STM32F070CB/rb/c6/f6 microcontrollers include devices in three different packages ranging from 20 pins to 64 pins. depending on the device chosen, different sets of peripherals are included. the description below provides an overview of the complete range of STM32F070CB/rb/c6/f6 peripherals proposed. these features make the STM32F070CB/rb/c6 /f6 microcontrollers suitable for a wide range of applications such as application cont rol and user interfaces, handheld equipment, a/v receivers and digital tv, pc peripherals , gaming and gps platforms, industrial applications, plcs, inve rters, printers, scanners, alarm systems, video intercoms, and hvacs. description stm32 f070cb/rb/c6/f6 10/83 docid027114 rev 3 table 1. STM32F070CB/rb/c6/f6 family d evice features and peripheral counts peripheral stm32f070f6 stm32f070c6 STM32F070CB stm32f070rb flash (kbytes) 32 128 sram (kbytes) 6 16 timers advanced control 1 (16-bit) general purpose 4 (16-bit) 5 (16-bit) basic - 2 (16-bit) comm. interfaces spi 1 2 i 2 c1 2 usart 2 4 usb 1 12-bit adc (number of channels) 1 (9 ext. + 2 int.) 1 (10 ext. + 2 int.) 1 (10 ext. + 2 int.) 1 (16 ext. + 2 int.) gpios 15 37 37 51 max. cpu frequency 48 mhz operating voltage 2.4 to 3.6 v operating temperature ambient operating temper ature: -40c to 85c junction temperature: -40c to 105c packages tssop20 lqf p48 lqfp48 lqfp64 docid027114 rev 3 11/83 STM32F070CB/rb/c6/f6 description 23 figure 1. block diagram 0 6 y 9 f k d q q h o v f r p s o f k d q q h o v % 5 . ( 7 5 l q s x w d v $ ) # 9 ' ' # 9 ' ' $ 6 \ v w h p d q g s h u l s k h u d o f o r f n v 3 $ > @ 3 % > @ 3 & > @ $ ) 0 2 6 , 0 , 6 2 6 & . 1 6 6 d v $ ) # 9 ' ' $ 9 ' ' $ 9 6 6 $ 6 : & / . 6 : ' , 2 d v $ ) [ $ ' l q s x w 2 6 & b , 1 2 6 & b 2 8 7 2 6 & b , 1 2 6 & b 2 8 7 7 $ 0 3 ( 5 5 7 & $ / $ 5 0 2 8 7 + 6 , + 6 , / 6 , 3 / / & / . , 5 b 2 8 7 d v $ ) f k d q q h o f r p s o % 5 . d v $ ) f k d q q h o f r p s o % 5 . d v $ ) f k d q q h o d v $ ) f k ( 7 5 d v $ ) * 3 ' 0 $ f k d q q h o v & 2 5 7 ( ; 0 & 3 8 i 0 $ ; 0 + ] 6 h u l d o : l u h ' h e x j 1 9 , & ( ; 7 , 7 : . 8 3 6 3 , 6 3 , 6 < 6 & ) * , ) ' % * 0 & 8 : l q g r z : ' * $ 3 % $ + % & 5 & 5 ( 6 ( 7 & / 2 & . & 2 1 7 5 2 / 3 r z h u & r q w u r o o h u ; 7 $ / 2 6 & 0 + ] , q g : l q g r z : ' * 6 5 $ 0 . % . % 7 h p s v h q v r u , ) e l w $ ' & 5 7 & 5 7 & l q w h u i d f h 5 & 0 + ] 5 & 0 + ] 5 & n + ] 3 / / $ + % g h f r g h u ; 7 $ / n + ] 6 5 $ 0 f r q w u r o o h u % x v p d w u l [ ) o d v k p h p r u \ l q w h u i d f h ) o d v k * 3 / . % . % e l w 2 e o f k d q q h o v f r p s o % 5 . d v $ ) 5 ; 7 ; & 7 6 5 7 6 & . d v $ ) 5 ; 7 ; & 7 6 5 7 6 & . d v $ ) 5 ; 7 ; & 7 6 5 7 6 & . d v $ ) 5 ; 7 ; & 7 6 5 7 6 & . d v $ ) 6 & / 6 ' $ d v $ ) 6 & / 6 ' $ 6 0 % $ p $ ) 0 d v $ ) , & , & 7 , 0 ( 5 7 , 0 ( 5 * 3 , 2 s r u w ) * 3 , 2 s r u w ' * 3 , 2 s r u w & * 3 , 2 s r u w % * 3 , 2 s r u w $ 3 ' 3 ) > @ 6 8 3 3 / < 6 8 3 ( 5 9 , 6 , 2 1 3 2 : ( 5 # 9 ' ' $ # 9 ' ' 9 ' ' 3 2 5 5 h v h w , q w 9 ' ' w r 9 9 6 6 1 5 6 7 9 ' ' $ 9 6 6 $ 9 ' ' 3 2 5 3 ' 5 9 2 / 7 5 ( * 9 w r 9 8 6 $ 5 7 8 6 $ 5 7 8 6 $ 5 7 8 6 $ 5 7 7 , 0 ( 5 7 , 0 ( 5 7 , 0 ( 5 7 , 0 ( 5 7 , 0 ( 5 3 : 0 7 , 0 ( 5 ' ' # 9 ' ' 8 6 % 3 + < 8 6 % 6 5 $ 0 % 3 r z h u g r p d l q r i d q d o r j e o r f n v 9 ' ' 9 ' ' $ 0 2 6 , 0 , 6 2 6 & . 1 6 6 d v $ ) functional overview STM32F070CB/rb/c6/f6 12/83 docid027114 rev 3 3 functional overview 3.1 arm ? -cortex ? -m0 core with embedded flash and sram the arm ? cortex ? -m0 processor is the latest generat ion of arm processors for embedded systems. it has been developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. the arm ? cortex ? -m0 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the stm32f0xx family has an embedded arm core and is therefore compatible with all arm tools and software. figure 1 shows the general block diagram of the device family. 3.2 memories the device has the following features: ? 6 to 16 kbytes of embedded sram access ed (read/write) at cpu clock speed with 0 wait states and featuring embedded parity checking with exception generation for fail- critical applications. ? the non-volatile memory is divided into two arrays: ? 32 to 128 kbytes of embedded flash memory for programs and data ? option bytes the option bytes are used to write-protect the memory (with 4 kb granularity) and/or readout-protect the whole memory with the following options: ? level 0: no readout protection ? level 1: memory readout protection, th e flash memory cannot be read from or written to if either debug features ar e connected or boot in ram is selected ? level 2: chip readout protection, debug features (cortex ? -m0 serial wire) and boot in ram selection disabled 3.3 boot modes at startup, the boot pin and boot selector opti on bit are used to select one of the three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart on pins pa14/pa15 or pa9/pa10. docid027114 rev 3 13/83 STM32F070CB/rb/c6/f6 functional overview 23 3.4 cyclic redundancy che ck calculation unit (crc) the crc (cyclic redundancy check) calculati on unit is used to get a crc code using a configurable generator polynomial value and size. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. 3.5 power management 3.5.1 power supply schemes ? v dd = 2.4 to 3.6 v: external power supply for i/os and the internal regulator. provided externally through vdd pins. ? v dda = from v dd to 3.6 v: external analog power supply for adc, reset blocks, rcs and pll. the v dda voltage level must be always greater or equal to the v dd voltage level and must be provided first. for more details on how to connect power pins, refer to figure 9: power supply scheme . 3.5.2 power supply supervisors the device has integrated power-on reset (por) and power-down reset (pdr) circuits. they are always active, and ensure proper operation above a threshold of 2 v. the device remains in reset mode when the monitored supply voltage is below a specified threshold, v por/pdr , without the need for an external reset circuit. ? the por monitors only the v dd supply voltage. during the startup phase it is required that v dda should arrive first and be greater than or equal to v dd . ? the pdr monitors both the v dd and v dda supply voltages, however the v dda power supply supervisor can be disabled (by programming a dedicated option bit) to reduce the power consumption if the app lication design ensures that v dda is higher than or equal to v dd . 3.5.3 voltage regulator the regulator has two operating modes and it is always enabled after reset. ? main (mr) is used in normal operating mode (run). ? low power (lpr) can be used in stop mode where the power demand is reduced. in standby mode, it is put in po wer down mode. in this mode, the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and sram are lost). functional overview STM32F070CB/rb/c6/f6 14/83 docid027114 rev 3 3.5.4 low-power modes the STM32F070CB/rb/c6/f6 microcontrollers support three low-power modes to achieve the best compromise between low power cons umption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode stop mode achieves very low power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled. the volt age regulator can also be put either in normal or in low power mode. the device can be woken up from stop mode by any of the exti lines. the exti line source can be one of the 16 external lines and rtc. ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillato rs are also switched off. after entering standby mode, sram and register contents are lost except for registers in the rtc domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pins, or an rtc event occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering stop or standby mode. 3.6 clocks and startup system clock selection is perf ormed on startup, however the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an external 4-32 mhz clock can be selected, in which case it is monitored for fa ilure. if failure is detected, th e system automatically switches back to the internal rc oscillator. a software interrupt is genera ted if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example on failure of an indirectly used extern al crystal, resona tor or oscillator). several prescalers allow the ap plication to configure the fr equency of the ahb and the apb domains. the maximum freq uency of the ahb and t he apb domains is 48 mhz. docid027114 rev 3 15/83 STM32F070CB/rb/c6/f6 functional overview 23 figure 2. clock tree 3.7 general-purpose inputs/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. the i/o configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. 0 6 y 9 2 6 & b , 1 2 6 & b 2 8 7 2 6 & b , 1 2 6 & b 2 8 7 , : ' * 3 / / 0 8 / 0 & 2 0 d l q f o r f n r x w s x w 3 / / & / . + 6 , + 6 ( + & / . 3 / / & / . $ + % f r u h p h p r u \ ' 0 $ & r u w h [ ) & / . i u h h u x q f o r f n $ ' & d v \ q f k u r q r x v f o r f n l q s x w / 6 ( / 6 , + 6 , + 6 ( 5 7 & 3 / / 6 5 & 6 : 0 & 2 5 7 & & / . 5 7 & 6 ( / 6 < 6 & / . 7 , 0 ) / , 7 ) & / . ) o d v k p h p r u \ s u r j u d p p l q j l q w h u i d f h + 6 , + 6 , , & 8 6 $ 5 7 / 6 ( + 6 , 6 < 6 & / . 3 & / . 6 < 6 & / . + 6 , 3 & / . & r u w h [ v \ v w h p w l p h u $ 3 % s h u l s k h u d o v / 6 , / 6 ( 3 5 ( ' , 9 3 / / 1 2 ' , 9 0 & 2 3 5 ( w r 7 , 0 / 6 ( + 6 ( & 6 6 / h j h q g z k l w h f o r f n w u h h f r q w u r o h o h p h q w f o r f n o l q h f r q w u r o o l q h e o d f n f o r f n w u h h h o h p h q w 0 + ] + 6 ( 2 6 & 0 + ] + 6 , 5 & ? ? n + ] / 6 ( 2 6 & n + ] / 6 , 5 & 3 / / [ [ [ [ [ 8 6 $ 5 7 6 : 3 3 5 ( 3 3 5 ( + 3 5 ( , & 6 : 6 < 6 & / . + 6 , + 6 , 0 + ] + 6 , 5 & 8 6 % functional overview STM32F070CB/rb/c6/f6 16/83 docid027114 rev 3 3.8 direct memory a ccess controller (dma) the 5-channel general-purpose dma manages memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. the dma supports circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. each channel is connected to dedicated hardw are dma requests, with support for software trigger on each channel. configuration is made by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: spi, i2c, usart, all timx timers (except tim14) and adc. 3.9 interrupts and events 3.9.1 nested vectored interrupt controller (nvic) the stm32f0xx family embeds a nested vectored interrupt controller able to handle up to 32 maskable interrupt channels (not including the 16 interrupt lines of cortex ? -m0) and 4 priority levels. ? closely coupled nvic gives lo w latency interrupt processing ? interrupt entry vector table address passed directly to the core ? closely coupled nvic core interface ? allows early processing of interrupts ? processing of late arriving higher priority interrupts ? support for tail-chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimal interrupt latency. 3.9.2 extended interrupt/event controller (exti) the extended interrupt/event co ntroller consists of 32 edge det ector lines used to generate interrupt/event requ ests and wake-up the system. ea ch line can be independently configured to select the trig ger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains t he status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal clock period. up to 51 gpios can be connected to the 16 external interrupt lines. docid027114 rev 3 17/83 STM32F070CB/rb/c6/f6 functional overview 23 3.10 analog to digital converter (adc) the 12-bit analog to digital converter has up to 16 external and two internal (temperature sensor, voltage reference measurement) channel s and performs conversions in single-shot or scan modes. in scan mode, automatic conv ersion is performed on a selected group of analog inputs. the adc can be served by the dma controller. an analog watchdog feature allows very precis e monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. 3.10.1 temperature sensor the temperature sensor (ts) generates a voltage v sense that varies linearly with temperature. the temperature sensor is internally connec ted to the adc_in16 input channel which is used to convert the sensor output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. to improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by st. the te mperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode. 3.10.2 internal voltage reference (v refint ) the internal voltage reference (v refint ) provides a stable (bandgap) voltage output for the adc. v refint is internally connected to the adc_in 17 input channel. the precise voltage of v refint is individually measured for each part by st during production test and stored in the system memory area. it is accessible in read-only mode. table 2. temperature sensor calibration values calibration value name description memory address ts_cal1 ts adc raw data acquired at a temperature of 30 c ( 5 c), v dda = 3.3 v ( 10 mv) 0x1fff f7b8 - 0x1fff f7b9 table 3. internal voltage reference calibration values calibration value name description memory address vrefint_cal raw data acquired at a temperature of 30 c ( 5 c), v dda = 3.3 v ( 10 mv) 0x1fff f7ba - 0x1fff f7bb functional overview STM32F070CB/rb/c6/f6 18/83 docid027114 rev 3 3.11 timers and watchdogs the STM32F070CB/rb/c6/f6 devices include up to five general-purpose timers, two basic timers and one advanced control timer. table 4 compares the features of the different timers. 3.11.1 advanced-c ontrol timer (tim1) the advanced-control timer (tim1) can be seen as a three-phase pwm multiplexed on six channels. it has complementary pwm outputs with programmable inserted dead times. it can also be seen as a complete general-purpose timer. the four independent channels can be used for: ? input capture ? output compare ? pwm generation (edge or center-aligned modes) ? one-pulse mode output if configured as a standard 16-bit timer, it has the same features as the timx timer. if configured as the 16-bit pw m generator, it has full modu lation capability (0-100%). the counter can be frozen in debug mode. many features are shared with those of the standard timers which have the same architecture. the advanced control timer can t herefore work together with the other timers via the timer link feature for sy nchronization or event chaining. table 4. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/compare channels complementary outputs advanced control tim1 16-bit up, down, up/down any integer between 1 and 65536 yes 4 3 general purpose tim3 16-bit up, down, up/down any integer between 1 and 65536 yes 4 - tim14 16-bit up any integer between 1 and 65536 no 1 - tim15 (1) 16-bit up any integer between 1 and 65536 yes 2 - tim16, tim17 16-bit up any integer between 1 and 65536 yes 1 1 basic tim6, (1) tim7 (1) 16-bit up any integer between 1 and 65536 yes 0 - 1. not available on stm32f070x6 devices. docid027114 rev 3 19/83 STM32F070CB/rb/c6/f6 functional overview 23 3.11.2 general-purpose ti mers (tim3, tim14..17) there are five synchronizable general-purpose timers embedded in the STM32F070CB/rb/c6/f6 devices (see table 4 for differences). each general-purpose timer can be used to generate pwm outputs, or as simple time base. tim3 STM32F070CB/rb/c6/f6 devices feature one synchronizable 4-channel general-purpose timer. tim3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. it features four independent channels each fo r input capture/output compare, pwm or one-pulse mode output. this gives up to 12 input captures/output compares/pwms on the largest packages. the tim3 general-purpose timer can work wi th the tim1 advanced-control timer via the timer link feature for synchronization or event chaining. tim3 has an independent dma request generation. this timer is capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. the counter can be frozen in debug mode. tim14 this timer is based on a 16-bit auto-re load upcounter and a 16-bit prescaler. tim14 features one single channel for input capture/output compare, pwm or one-pulse mode output. its counter can be frozen in debug mode. tim15, tim16 and tim17 these timers are based on a 16-bit auto -reload upcounter and a 16-bit prescaler. tim15 has two independent channels, wher eas tim16 and tim17 feature one single channel for input capture/output compare, pwm or one-pulse mode output. the tim15, tim16 and tim17 timers can wo rk together, and tim15 can also operate withtim1 via the timer link feature for synchronization or event chaining. tim15 can be synchronized with tim16 and tim17. tim15, tim16 and tim17 have a complement ary output with dead-time generation and independent dma request generation. their counters can be frozen in debug mode. 3.11.3 basic time rs tim6 and tim7 these timers can be used as a generic 16-bit time base. 3.11.4 independent watchdog (iwdg) the independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and standby modes. it functional overview STM32F070CB/rb/c6/f6 20/83 docid027114 rev 3 can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. 3.11.5 system win dow watchdog (wwdg) the system window watchdog is based on a 7-bit downcounter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the apb clock (pclk). it has an early warning interrupt capability and the counter can be frozen in debug mode. 3.11.6 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: ? a 24-bit down counter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0 ? programmable clock source (hclk or hclk/8) 3.12 real-time clock (rtc) the rtc is an independent bcd timer/counter. its main features are the following: ? calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format. ? automatic correction for 28, 29 (leap year), 30, and 31 day of the month. ? programmable alarm with wake up fr om stop and standby mode capability. ? periodic wakeup unit with programmable resolution and period. ? on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize the rtc with a master clock. ? digital calibration circuit with 1 ppm resolu tion, to compensate for quartz crystal inaccuracy. ? tow anti-tamper detection pins with programmable filter. the mcu can be woken up from stop and standby modes on tamper event detection. ? timestamp feature which can be used to save the calendar content. this function can be triggered by an event on the timestamp pin, or by a tamper event. the mcu can be woken up from stop and standby modes on timestamp event detection. ? reference clock detection: a more precise se cond source clock (50 or 60 hz) can be used to enhance the calendar precision. the rtc clock sources can be: ? a 32.768 khz external crystal ? a resonator or oscillator ? the internal low-power rc oscillator (typical frequency of 40 khz) ? the high-speed external clock divided by 32 docid027114 rev 3 21/83 STM32F070CB/rb/c6/f6 functional overview 23 3.13 inter-integrated circuit interfaces (i 2 c) up to two i2c interfaces (i2c1 and i2c2) can operate in multimaster or slave modes. both can support standard mode (up to 100 kbit/s) or fast mode (up to 400 kbit/s). i2c1 also supports fast mode plus (up to 1 mbit/s), with 20 ma output drive. both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (two addresses, one with configurable mask). they also include programmable analog and digital noise filters. in addition, i2c1 provides hardware su pport for smbus 2.0 and pmbus 1.1: arp capability, host notify prot ocol, hardware crc ( pec) generation/verification, timeouts verifications and alert protocol management. the i2c interfaces can be served by the dma controller. refer to table 6 for the differences be tween i2c1 and i2c2. 3.14 universal synchronous/asyn chronous receiver/transmitter (usart) the device embeds up to four universal syn chronous/asynchronous receivers/transmitters that communicate at speeds of up to 6 mbit/s. table 5. comparison of i2c analog and digital filters - analog filter digital filter pulse width of suppressed spikes 50 ns programmable length from 1 to 15 i2c peripheral clocks benefits available in stop mode 1. extra filtering capability vs. standard requirements. 2. stable length drawbacks variations depending on temperature, voltage, process - table 6. STM32F070CB/rb/c6/f6 i 2 c implementation (1) 1. x = supported. i2c features i2c1 i2c2 (2) 2. only available on stm32f070xb devices. 7-bit addressing mode x x 10-bit addressing mode x x standard mode (up to 100 kbit/s) x x fast mode (up to 400 kbit/s) x x fast mode plus (up to 1 mbit/s), with 20ma output drive i/os x - independent clock x - smbus x - wakeup from stop - - functional overview STM32F070CB/rb/c6/f6 22/83 docid027114 rev 3 table 7 gives an overview of features as implem ented on the available usart interfaces. all usart interfaces can be served by the dma controller. 3.15 serial peripheral interface (spi) up to two spis are able to commu nicate up to 18 mbit/s in slave and master modes in full- duplex and half-duplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. spi1 and spi2 are identical and implement the set of features shown in the following table. table 7. stm32f70x0 usart implementation (1) 1. x = supported. usart modes/ features stm32f070x6 stm32f070xb usart1 usart2 usart1 usart2 usart3 usart4 hardware flow control for modem xxxxx continuous communication using dma xxxx - multiprocessor communication xxxxx synchronous mode xxxxx smartcard mode ----- single-wire half-duplex communication xxxxx irda sir endec block ----- lin mode ----- dual clock domain and wakeup from stop mode ----- receiver timeout interrupt x-x- - modbus communication ----- auto baud rate detection (supported modes) 4-4- - driver enable xxxxx usart data length 7, 8 and 9 bits docid027114 rev 3 23/83 STM32F070CB/rb/c6/f6 functional overview 23 3.16 universal serial bus (usb) the STM32F070CB/rb/c6/f6 embeds a full-s peed usb device peripheral compliant with the usb specification version 2.0. the inte rnal usb phy supports usb fs signaling, embedded dp pull-up and also battery charging detection according to battery charging specification revision 1.2. t he usb interface implements a full-speed (12 mbit/s) function interface with added support for usb 2.0 link power management. it has software- configurable endpoint setting with packet memory up-to 1 kb and suspend/resume support. it requires a precise 48 mhz clock which can be generated from the internal main pll (the clock source must use an hse crystal oscillator). 3.17 serial wire debug port (sw-dp) an arm sw-dp interface is provided to allow a serial wire debugging tool to be connected to the mcu. table 8. STM32F070CB/rb/c6/f6 spi implementation (1) 1. x = supported. spi features spi1 spi2 (2) 2. available on stm32f070xb only. hardware crc calculation x x rx/tx fifo x x nss pulse mode x x ti mode x x pinouts and pin descriptions STM32F070CB/rb/c6/f6 24/83 docid027114 rev 3 4 pinouts and pin descriptions figure 3. lqfp64 64-pin package pinout (top view) figure 4. lqfp48 48-pin package pinout (top view) 9 ' ' 3 & 2 6 & b , 1 3 ) 2 6 & b , 1 1 5 6 7 3 & 3 & 3 & 3 & 9 6 6 $ 9 ' ' $ 3 $ 3 $ 3 $ 9 ' ' 3 % 3 % % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 ' 3 & 3 & 3 & 3 $ 3 $ 9 ' ' 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 & 3 & 3 % 3 % 3 % 3 % 3 $ 9 6 6 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 % 3 % 3 % 3 % 3 % / 4 ) 3 3 & 9 ' ' 9 6 6 9 ' ' 9 6 6 3 ) 2 6 & b 2 8 7 3 & 2 6 & b 2 8 7 0 6 9 0 6 9 / 4 ) 3 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % 3 % 9 6 6 9 ' ' 9 ' ' 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % 9 ' ' 1 5 6 7 9 6 6 $ 9 ' ' $ 3 $ 3 $ 3 $ 9 ' ' 9 6 6 3 % 3 % % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 $ 3 $ 3 & 3 & 2 6 & b , 1 3 ) 2 6 & b , 1 3 ) 2 6 & b 2 8 7 3 & 2 6 & b 2 8 7 docid027114 rev 3 25/83 STM32F070CB/rb/c6/f6 pinouts and pin descriptions 29 figure 5. tssop20 20-pin package pinout (top view) 3 ) 2 6 & b , 1 % 2 2 7 3 ) 2 6 & b 2 8 7 1 5 6 7 9 ' ' $ 3 $ 9 ' ' 3 $ 3 $ 3 $ 3 % 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ > 3 $ @ 3 $ > 3 $ @ 0 6 9 table 9. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets belo w the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o ftf 5 v tolerant i/o, fm+ capable tta 3.3 v tolerant i/o directly connected to adc tc standard 3.3 v i/o b dedicated boot0 pin rst bidirectional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset. pin functions alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabled through peripheral registers pinouts and pin descriptions STM32F070CB/rb/c6/f6 26/83 docid027114 rev 3 table 10. stm32f070xb/6 pin definitions pin numbers pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp48 tssop20 alternate functions a dditional functions 1 1 - vdd s - - digital power supply 22 - pc13 i/otc (1) (2) - wkup2, rtc_tamp1, rtc_ts, rtc_out 33 - pc14-osc32_in (pc14) i/o tc (1) (2) - osc32_in 44 - pc15- osc32_out (pc15) i/o tc (1) (2) - osc32_out 552 pf0-osc_in (pf0) i/o ft - i2c1_sda (3) osc_in 663 pf1-osc_out (pf1) i/o ft - i2c1_scl (3) osc_out 7 7 4 nrst i/o rst - device reset input / internal reset output (active low) 8 - - pc0 i/o tta - eventout adc_in10 9 - - pc1 i/o tta - eventout adc_in11 10 - - pc2 i/o tta - spi2_miso, eventout adc_in12 11 - - pc3 i/o tta - spi2_mosi, eventout adc_in13 12 8 - vssa s - - analog ground 13 9 5 vdda s - - analog power supply 14 10 6 pa0 i/o tta (4) usart2_cts, usart4_tx rtc_ tamp2, wkup1, adc_in0, 15 11 7 pa1 i/o tta (4) usart2_rts, tim15_ch1n, usart4_rx, eventout adc_in1 16 12 8 pa2 i/o tta (4) usart2_tx, tim15_ch1 adc_in2, wkup4 17 13 9 pa3 i/o tta (4) usart2_rx, tim15_ch2 adc_in3 18 - - vss s - - ground 19 - - vdd s - - digital power supply 20 14 10 pa4 i/o tta - spi1_nss, tim14_ch1, usart2_ck, usb_noe (3) adc_in4 21 15 11 pa5 i/o tta - spi1_sck adc_in5 docid027114 rev 3 27/83 STM32F070CB/rb/c6/f6 pinouts and pin descriptions 29 22 16 12 pa6 i/o tta (4) spi1_miso, tim3_ch1, tim1_bkin, tim16_ch1, eventout, usart3_cts adc_in6 23 17 13 pa7 i/o tta - spi1_mosi, tim3_ch2, tim14_ch1, tim1_ch1n, tim17_ch1, eventout adc_in7 24 - - pc4 i/o tta (4) eventout, usart3_tx adc_in14 25 - - pc5 i/o tta (4) usart3_rx adc_in15, wkup5 26 18 - pb0 i/o tta (4) tim3_ch3, tim1_ch2n, eventout, usart3_ck adc_in8 27 19 14 pb1 i/o tta (4) tim3_ch4, usart3_rts, tim14_ch1, tim1_ch3n adc_in9 28 20 - pb2 i/o ft - - - 29 21 - pb10 i/o ft (4) spi2_sck, usart3_tx - 30 22 - pb11 i/o ft (4) usart3_rx, eventout, i2c2_sda - 31 23 15 vss s - - ground 32 24 16 vdd s - - digital power supply 33 25 - pb12 i/o ft (4) tim1_bkin, tim15_bkin, spi2_nss, eventout, usart3_ck - 34 26 - pb13 i/o ftf (4) spi2_sck, i2c2_scl, tim1_ch1n, usart3_cts - 35 27 - pb14 i/o ftf (4) spi2_miso, i2c2_sda, tim1_ch2n, tim15_ch1, usart3_rts - 36 28 - pb15 i/o ft (4) spi2_mosi, tim1_ch3n, tim15_ch1n, tim15_ch2 wkup7, rtc_refin 37 - - pc6 i/o ft - tim3_ch1 - 38 - - pc7 i/o ft - tim3_ch2 - 39 - - pc8 i/o ft - tim3_ch3 - 40 - - pc9 i/o ft - tim3_ch4 - table 10. stm32f070xb/6 pin definitions (continued) pin numbers pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp48 tssop20 alternate functions a dditional functions pinouts and pin descriptions STM32F070CB/rb/c6/f6 28/83 docid027114 rev 3 41 29 - pa8 i/o ft - usart1_ck, tim1_ch1, eventout, mco - 42 30 17 pa9 i/o ft (4) usart1_tx, tim1_ch2, tim15_bkin, i2c1_scl (3) - 43 31 18 pa10 i/o ft - usart1_rx, tim1_ch3, tim17_bkin, i2c1_sda (3) - 44 32 17 (5) pa11 i/o ft - usart1_cts, tim1_ch4, eventout usb_dm 45 33 18 (5) pa12 i/o ft - usart1_rts, tim1_etr, eventout usb_dp 46 34 19 pa13 i/o ft (6) ir_out, swdio, usb_noe - 47 35 - vss s - - ground 48 36 - vdd s - - digital power supply 49 37 20 pa14 i/o ft - usart2_tx, swclk - 50 38 - pa15 i/o ft (4) spi1_nss, usart2_rx, usart4_rts, eventout - 51 - - pc10 i/o ft (4) usart3_tx, usart4_tx - 52 - - pc11 i/o ft (4) usart3_rx, usart4_rx - 53 - - pc12 i/o ft (4) usart3_ck, usart4_ck - 54 - - pd2 i/o ft (4) tim3_etr, usart3_rts - 55 39 - pb3 i/o ft - spi1_sck, eventout - 56 40 - pb4 i/o ft - spi1_miso, tim17_bkin, tim3_ch1, eventout - 57 41 - pb5 i/o ft (4) spi1_mosi, i2c1_smba, tim16_bkin, tim3_ch2 wkup6 58 42 - pb6 i/o ftf - i2c1_scl, usart1_tx, tim16_ch1n - table 10. stm32f070xb/6 pin definitions (continued) pin numbers pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp48 tssop20 alternate functions a dditional functions docid027114 rev 3 29/83 STM32F070CB/rb/c6/f6 pinouts and pin descriptions 29 59 43 - pb7 i/o ftf (4) i2c1_sda, usart1_rx, usart4_cts, tim17_ch1n - 60 44 1 boot0 i b - boot memory selection 61 45 - pb8 i/o ftf - i2c1_scl, tim16_ch1 - 62 46 - pb9 i/o ftf (4) spi2_nss, i2c1_sda, ir_out, tim17_ch1, eventout - 63 47 - vss s - - ground 64 48 - vdd s - - digital power supply 1. pc13, pc14 and pc15 are supplied through the power switch. si nce the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf. - these gpios must not be used as current sources (e.g. to drive an led). 2. after the first rtc domain power-up, pc13, pc14 and pc15 operate as gpios. their function then depends on the content of the rtc registers which are not reset by the syst em reset. for details on how to manage these gpios, refer to the rtc domain and rtc register descriptions in the reference manual. 3. available on stm32f070c6/f6 devices only. 4. tim15, i2c2, wkup4, wkup5, wkup6, wkup7, spi2, usart3 and usart4 are available on STM32F070CB/rb devices only. 5. on stm32f070c6/f6 devices, pin pair pa11/12 can be remapped instead of pin pair pa9/10 using syscfg_cfgr1 register. 6. after reset, these pins are configured as swdio and swcl k alternate functions, and the internal pull-up on the swdio pin and the internal pull-down on the swclk pin are activated. table 10. stm32f070xb/6 pin definitions (continued) pin numbers pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp48 tssop20 alternate functions a dditional functions STM32F070CB/rb/c6/f6 30/83 docid027114 rev 3 table 11. alternate functions selected through gpioa_afr registers for port a pin name af0 af1 af2 af3 af4 af5 af6 af7 pa0 - usart2_cts - - usart4_tx (1) 1. available on STM32F070CB/rb devices only. --- pa1 eventout usart2_rts - - usart4_rx (1) tim15_ch1n (1) -- pa2 tim15_ch1 (1) usart2_tx - - - - - - pa3 tim15_ch2 (1) usart2_rx - - - - - - pa4 spi1_nss usart2_ck usb_noe (2) 2. available on stm32f070c6/f6 devices only. - tim14_ch1 - - - pa5 spi1_sck - - - - - - - pa6 spi1_miso tim3_ch1 ti m1_bkin - usart3_cts (1) tim16_ch1 eventout - pa7 spi1_mosi tim3_ch2 tim1_ch1 n - tim14_ch1 tim17_ch1 eventout - pa8 mco usart1_ck tim1_ch1 eventout - - - - pa9 tim15_bkin (1) usart1_tx tim1_ch2 - i2c1_scl (2) --- pa10 tim17_bkin usart1_rx tim1_ch3 - i2c1_sda (2) --- pa11 eventout usart1_cts tim1_ch4 - - - - - pa12 eventout usart1_rts tim1_etr - - - - - pa13 swdio ir_out usb_noe - - - - - pa14 swclk usart2_tx - - - - - - pa15 spi1_nss usart2_rx - eventout usart4_rts (1) --- STM32F070CB/rb/c6/f6 docid027114 rev 3 31/83 table 12. alternate functions selected through gpiob_afr registers for port b pin name af0 af1 af2 af3 af4 af5 pb0 eventout tim3_ch3 tim1_ch2n - usart3_ck (1) 1. available on stm32f070xb devices only. - pb1 tim14_ch1 tim3_ch4 tim1_ch3n - usart3_rts (1) - pb2- ---- - pb3 spi1_sck eventout - - - - pb4 spi1_miso tim3_ch1 eventout - - tim17_bkin pb5 spi1_mosi tim3_ch2 tim16_bkin i2c1_smba - - pb6 usart1_tx i2c1_scl tim16_ch1n - - - pb7 usart1_rx i2c1_sda tim17_ch1n - usart4_cts (1) - pb8 - i2c1_scl tim16_ch1 - - - pb9 ir_out i2c1_sda tim17_ch1 eventout - spi2_nss (1) pb10 - i2c2_scl (1) - - usart3_tx (1) spi2_sck (1) pb11 eventout i2c2_sda (1) - - usart3_rx (1) - pb12 spi2_nss (1) eventout tim1_bkin - usart3_ck (1) tim15_bkin (1) pb13 spi2_sck (1) - tim1_ch1n - usart3_cts (1) i2c2_scl (1) pb14 spi2_miso (1) tim15_ch1 tim1_ch2n - usart3_rts (1) i2c2_sda (1) pb15 spi2_mosi (1) tim15_ch2 tim1_ch3n tim15_ch1n (1) -- STM32F070CB/rb/c6/f6 32/83 docid027114 rev 3 table 13. alternate functions selected through gpioc_afr registers for port c pin name af0 (1) af1 (1) pc0 eventout (1) - pc1 eventout (1) - pc2 eventout (1) spi2_miso (1) pc3 eventout (1) spi2_mosi (1) pc4 eventout (1) usart3_tx (1) 1. available on stm32f070xb devices only. pc5 - usart3_rx (1) pc6 tim3_ch1 (1) - pc7 tim3_ch2 (1) - pc8 tim3_ch3 (1) - pc9 tim3_ch4 (1) - pc10 usart4_tx (1) usart3_tx (1) pc11 usart4_rx (1) usart3_rx (1) pc12 usart4_ck (1) usart3_ck (1) pc13 - - pc14 - - pc15 - - table 14. alternate functions selected through gpiod_afr registers for port d pin name af0 (1) 1. available on stm32f070xb devices only. af1 (1) pd2 tim3_etr (1) - table 15. alternate functions selected through gpiof_afr registers for port f pin name af0 af1 pf0 - i2c1_sda (1) 1. available on stm32f070x6 devices only. pf1 - i2c1_scl (1) docid027114 rev 3 33/83 STM32F070CB/rb/c6/ f6 memory mapping 35 5 memory mapping figure 6. stm32f070 cb/rb/c6/f6 memory map 1. the start address of the system memory is 0x1fff c800 on stm32f070xb devices and 0x1fff c400 on stm32f070x6 devices. 0 6 y 9 ! ( " [ ) ) ) ) ) ) ) ) 3 h u l s k h u d o v 6 5 $ 0 ) o d v k p h p r u \ 2 e s e r v e d 6 \ v w h p p h p r u \ 2 s w l r q % \ w h v [ ( & l a s h s y s t e m m e m o r y o r 3 2 ! - d e p e n d i n g o n " / / 4 c o n f i g u r a t i o n [ [ ( [ & [ $ [ [ [ [ [ [ [ [ ) ) ) & [ [ ) ) ) ) [ ) ) ) ) ) ) ) [ 2 e s e r v e d & 2 ' ( ! 0 " ! 0 " 2 e s e r v e d [ [ [ [ 2 e s e r v e d [ ! ( " [ 2 e s e r v e d [ ) ) [ ) ) & r u w h [ 0 l q w h u q d o s h u l s k h u d o v 2 e s e r v e d [ ) ) ) ) & 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d memory mapping stm 32f070cb/rb/c6/f6 34/83 docid027114 rev 3 table 16. STM32F070CB/rb/c6/f6 peripheral register boundary addresses bus boundary address size peripheral - 0x4800 1800 - 0x5fff ffff ~384 mb reserved ahb2 0x4800 1400 - 0x4800 17ff 1 kb gpiof 0x4800 1000 - 0x4800 13ff 1 kb reserved 0x4800 0c00 - 0x4800 0fff 1 kb gpiod 0x4800 0800 - 0x4800 0bff 1 kb gpioc 0x4800 0400 - 0x4800 07ff 1 kb gpiob 0x4800 0000 - 0x4800 03ff 1 kb gpioa - 0x4002 4400 - 0x47ff ffff ~128 mb reserved ahb1 0x4002 3400 - 0x4002 43ff 4 kb reserved 0x4002 3000 - 0x4002 33ff 1 kb crc 0x4002 2400 - 0x4002 2fff 3 kb reserved 0x4002 2000 - 0x4002 23ff 1 kb flash interface 0x4002 1400 - 0x4002 1fff 3 kb reserved 0x4002 1000 - 0x4002 13ff 1 kb rcc 0x4002 0400 - 0x4002 0fff 3 kb reserved 0x4002 0000 - 0x4002 03ff 1 kb dma - 0x4001 8000 - 0x4001 ffff 32 kb reserved apb 0x4001 5c00 - 0x4001 7fff 9 kb reserved 0x4001 5800 - 0x4001 5bff 1 kb dbgmcu 0x4001 4c00 - 0x4001 57ff 3 kb reserved 0x4001 4800 - 0x4001 4bff 1 kb tim17 0x4001 4400 - 0x4001 47ff 1 kb tim16 0x4001 4000 - 0x4001 43ff 1 kb tim15 0x4001 3c00 - 0x4001 3fff 1 kb reserved 0x4001 3800 - 0x4001 3bff 1 kb usart1 0x4001 3400 - 0x4001 37ff 1 kb reserved 0x4001 3000 - 0x4001 33ff 1 kb spi1 0x4001 2c00 - 0x4001 2fff 1 kb tim1 0x4001 2800 - 0x4001 2bff 1 kb reserved 0x4001 2400 - 0x4001 27ff 1 kb adc 0x4001 0800 - 0x4001 23ff 7 kb reserved 0x4001 0400 - 0x4001 07ff 1 kb exti 0x4001 0000 - 0x4001 03ff 1 kb syscfg - 0x4000 8000 - 0x4000 ffff 32 kb reserved docid027114 rev 3 35/83 STM32F070CB/rb/c6/ f6 memory mapping 35 apb 0x4000 7400 - 0x4000 7fff 3 kb reserved 0x4000 7000 - 0x4000 73ff 1 kb pwr 0x4000 6c00 - 0x4000 6fff 1 kb reserved 0x4000 6400 - 0x4000 67ff 2 kb reserved 0x4000 6000 - 0x4000 63ff 1 kb usb ram 0x4000 5800 - 0x4000 5bff 1 kb i2c2 (1) 0x4000 5400 - 0x4000 57ff 1 kb i2c1 0x4000 5000 - 0x4000 53ff 3 kb reserved 0x4000 4c00 - 0x4000 4fff 1 kb usart4 (1) 0x4000 4800 - 0x4000 4bff 1 kb usart3 (1) 0x4000 4400 - 0x4000 47ff 1 kb usart2 0x4000 3c00 - 0x4000 43ff 2 kb reserved 0x4000 3800 - 0x4000 3bff 1 kb spi2 (1) 0x4000 3400 - 0x4000 37ff 1 kb reserved 0x4000 3000 - 0x4000 33ff 1 kb iwdg 0x4000 2c00 - 0x4000 2fff 1 kb wwdg 0x4000 2800 - 0x4000 2bff 1 kb rtc 0x4000 2400 - 0x4000 27ff 1 kb reserved 0x4000 2000 - 0x4000 23ff 1 kb tim14 0x4000 1800 - 0x4000 1fff 2 kb reserved 0x4000 1400 - 0x4000 17ff 1 kb tim7 0x4000 1000 - 0x4000 13ff 1 kb tim6 0x4000 0800 - 0x4000 0fff 2 kb reserved 0x4000 0400 - 0x4000 07ff 1 kb tim3 0x4000 0000 - 0x4000 03ff 1 kb reserved 1. available on STM32F070CB/rb devices only. table 16. STM32F070CB/rb/c6/f6 peripheral register boundary addresses (continued) bus boundary address size peripheral electrical characteristics STM32F070CB/rb/c6/f6 36/83 docid027114 rev 3 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = v dda = 3.3 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 7 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 8 . figure 7. pin loading conditions figure 8. pin input voltage 0 6 9 0 & 8 s l q & s ) 0 6 9 0 & 8 s l q 9 , 1 docid027114 rev 3 37/83 STM32F070CB/rb/c6/f6 electrical characteristics 69 6.1.6 power supply scheme figure 9. power supply scheme caution: each power supply pair (v dd /v ss , v dda /v ssa etc.) must be decoupled with filtering ceramic capacitors as shown above. these capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the pcb to ensure the good functionality of the device. 0 6 y 9 9 ' ' / h y h o v k l i w h u , 2 o r j l f . h u q h o o r j l f & 3 8 ' l j l w d o 0 h p r u l h v / 6 ( 5 7 & : d n h x s o r j l f , 1 2 8 7 5 h j x o d w r u * 3 , 2 v [ q ) [ ? ) [ 9 6 6 [ 9 ' ' 9 & 2 5 ( 3 r z h u v z l w f k 9 ' ' , 2 $ ' & $ q d o r j 5 & v 3 / / ? 9 5 ( ) 9 5 ( ) 9 ' ' $ q ) ? ) 9 ' ' $ 9 6 6 $ electrical characteristics STM32F070CB/rb/c6/f6 38/83 docid027114 rev 3 6.1.7 current consumption measurement figure 10. current consum ption measurement scheme 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 17: voltage characteristics , table 18: current characteristics and table 19: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability. 0 6 9 9 ' ' 9 ' ' $ , ' ' , ' ' $ table 17. voltage characteristics (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. symbol ratings min max unit v dd ?v ss external main supply voltage -0.3 4.0 v v dda ?v ss external analog supply voltage -0.3 4.0 v v dd ?v dda allowed voltage difference for v dd > v dda -0.4v v in (2) 2. v in maximum must always be respected. refer to table 18: current characteristics for the maximum allowed injected current values. input voltage on ft and ftf pins v ss ? 0.3 v ddiox + 4.0 (3) 3. v ddiox is internally c onnected with vdd pin. v input voltage on tta pins v ss ? 0.3 4.0 v boot0 0 v ddiox + 4.0 (3) v input voltage on any other pin v ss ? 0.3 4.0 v | v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all the different ground pins -50mv v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.12: electrical sensitivity characteristics - docid027114 rev 3 39/83 STM32F070CB/rb/c6/f6 electrical characteristics 69 6.3 operating conditions 6.3.1 general operating conditions table 18. current characteristics symbol ratings max. unit i vdd total current into sum of all vdd power lines (source) (1) 120 ma i vss total current out of sum of all vss ground lines (sink) (1) -120 i vdd(pin) maximum current into each vdd power pin (source) (1) 100 i vss(pin) maximum current out of each vss ground pin (sink) (1) -100 i io(pin) output current sunk by any i/o and control pin 25 output current source by any i/o and control pin -25 i io(pin) total output current sunk by su m of all i/os and control pins (2) 80 total output current sourced by su m of all i/os and control pins (2) -80 i inj(pin) (3) injected current on ft and ftf pins -5/+0 (4) injected current on tc and rst pin 5 injected current on tta pins (5) 5 i inj(pin) total injected current (sum of all i/o and control pins) (6) 25 1. all main power (vdd, vdda) and ground (vss, vssa) pins must always be connected to the external power supply, in the permitted range. 2. this current consumption must be correctly distributed over all i/os and control pins. the total output current must not be sunk/sourced between two c onsecutive power supply pins referr ing to high pin count qfp packages. 3. a positive injection is induced by v in > v ddiox while a negative injection is induced by v in < v ss . i inj(pin) must never be exceeded. refer to table 17: voltage characteristics for the maximum allowed input voltage values. 4. positive injection is not possible on these i/os and does not occur for input voltages lower than the specified maximum value. 5. on these i/os, a positive injection is induced by v in > v dda . negative injection disturbs the analog performance of the device. see note (2) below table 51: adc accuracy . 6. when several inputs are submitted to a current injection, the maximum i inj(pin) is the absolute sum of the positive and negative injected currents (instantaneous values). table 19. thermal characteristics symbol ratings value unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 150 c table 20. general operating conditions symbol parameter conditions min max unit f hclk internal ahb clock frequency - 0 48 mhz f pclk internal apb clock frequency - 0 48 v dd standard operating voltage - 2.4 3.6 v electrical characteristics STM32F070CB/rb/c6/f6 40/83 docid027114 rev 3 6.3.2 operating conditions at power-up / power-down the parameters given in table 21 are derived from tests performed under the ambient temperature condition summarized in table 20 . 6.3.3 embedded reset and power control block characteristics the parameters given in table 22 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 20: general operating conditions . v dda analog operating voltage must have a potential equal to or higher than v dd 2.4 3.6 v v in i/o input voltage tc and rst i/o -0.3 v ddiox +0.3 v tta i/o -0.3 v dda +0.3 (2) ft and ftf i/o -0.3 5.5 (2) boot0 0 5.5 p d power dissipation at t a = 85 c for suffix 6 (1) lqfp64 - 455 mw lqfp48 - 364 tssop20 - 263 t a ambient temperature for the suffix 6 version maximum power dissipation -40 85 c low power dissipation (2) -40 105 t j junction temperature range suffix 6 version -40 105 c 1. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax . 2. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax (see section 7.4: thermal characteristics ). table 20. general operating conditions (continued) symbol parameter conditions min max unit table 21. operating conditions at power-up / power-down symbol parameter conditions min max unit t vdd v dd rise time rate - 0 s/v v dd fall time rate 20 t vdda v dda rise time rate - 0 v dda fall time rate 20 table 22. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v por/pdr (1) power on/power down reset threshold falling edge (2) 1.80 1.88 1.96 (3) v rising edge 1.84 (3) 1.92 2.00 v docid027114 rev 3 41/83 STM32F070CB/rb/c6/f6 electrical characteristics 69 6.3.4 embedded reference voltage the parameters given in table 23 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 20: general operating conditions . 6.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pi n loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 10: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to coremark code. v pdrhyst pdr hysteresis - - 40 - mv t rsttempo (4) reset temporization - 1.50 2.50 4.50 ms 1. the pdr detector monitors v dd and also v dda (if kept enabled in the opti on bytes). the por detector monitors only v dd . 2. the product behavior is guaranteed by design down to the minimum v por/pdr value. 3. data based on characterization results, not tested in production. 4. guaranteed by design, not tested in production. table 22. embedded reset and power control block characteristics (continued) symbol parameter conditions min typ max unit table 23. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage -40c < t a < +85c 1.2 1.23 1.25 v t start adc_in17 buffer startup time ---10 (1) s t s_vrefint adc sampling time when reading the internal reference voltage - 4 (1) --s v refint internal reference voltage spread over the temperature range v dda = 3 v - - 10 (1) 1. guaranteed by design, not tested in production. mv t coeff temperature coefficient - -100 (1) - 100 (1) ppm/c electrical characteristics STM32F070CB/rb/c6/f6 42/83 docid027114 rev 3 typical and maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in analog input mode ? all peripherals are disabled ex cept when explicitly mentioned ? the flash memory access time is adjusted to the f hclk frequency: ? 0 wait state and prefetch off from 0 to 24 mhz ? 1 wait state and prefetch on above 24 mhz ? when the peripherals are enabled f pclk = f hclk the parameters given in table 24 to table 26 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 20: general operating conditions . table 24. typical and maximum current consumption from v dd supply at v dd = 3.6 v symbol parameter conditions f hclk all peripherals enabled unit typ max @ t a (1) 85 c i dd supply current in run mode, code executing from flash hsi or hse clock, pll on 48 mhz 24.1 27.6 ma 24 mhz 12.4 14.4 hsi or hse clock, pll off 8 mhz 4.52 5.28 i dd supply current in run mode, code executing from ram hsi or hse clock, pll on 48 mhz 23.1 25.0 ma 24 mhz 11.5 13.6 hsi or hse clock, pll off 8 mhz 4.34 5.03 i dd supply current in sleep mode, code executing from flash or ram hsi or hse clock, pll on 48 mhz 15.0 17.3 ma 24 mhz 7.53 8.87 hsi or hse clock, pll off 8 mhz 2.95 3.41 1. data based on characterization results, not tested in production unles s otherwise specified. table 25. typical and maximum current consumption from the v dda supply symbol parameter conditions (1) f hclk v dda = 3.6 v unit typ max @ t a 85 c i dda supply current in run or sleep mode, code executing from flash or ram hse bypass, pll on 48 mhz 165 196 a hse bypass, pll off 8 mhz 3.6 5.2 1 mhz 3.6 5.2 hsi clock, pll on 48 mhz 245 279 hsi clock, pll off 8 mhz 83.4 95.3 docid027114 rev 3 43/83 STM32F070CB/rb/c6/f6 electrical characteristics 69 typical current consumption the mcu is placed under the following conditions: ? v dd = v dda = 3.3 v ? all i/o pins are in analog input configuration ? the flash access time is adjusted to f hclk frequency: ? 0 wait state and prefetch off from 0 to 24 mhz ? 1 wait state and prefetch on above 24 mhz ? when the peripherals are enabled, f pclk = f hclk ? pll is used for frequencies greater than 8 mhz ? ahb prescaler of 2, 4, 8 and 16 is used for the frequencies 4 mhz, 2 mhz, 1 mhz and 500 khz respectively 1. current consumption from the v dda supply is independent of whether the digital peripherals are enabled or disabled, being in run or sleep mode or executing from flash or ram. furthermore, when the pll is off, i dda is independent from the frequency. table 26. typical and maximum consumption in stop and standby modes symbol parameter conditions typ @v dd (v dd = v dda ) max (1) unit 3.6 v t a = 85 c i dd supply current in stop mode regulator in run mode, all oscillators off 15.9 49 a regulator in low-power mode, all oscillators off 3.7 33 supply current in standby mode lsi on and iwdg on 1.5 - i dda supply current in stop mode v dda monitoring on regulator in run or low- power mode, all oscillators off 2.8 3.6 supply current in standby mode lsi on and iwdg on 3.5 - lsi off and iwdg off 2.6 3.6 supply current in stop mode v dda monitoring off regulator in run or low- power mode, all oscillators off 1.5 - supply current in standby mode lsi on and iwdg on 2.2 - lsi off and iwdg off 1.4 - 1. data based on characterization results, not tested in production unless otherwise specified. electrical characteristics STM32F070CB/rb/c6/f6 44/83 docid027114 rev 3 i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up ge nerate current consumpt ion when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resi stors values given in table 45: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applie d. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input va lue. unless this spec ific configuration is required by the application, this supply curr ent consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an in termediate voltage level or switch inadvertently, as a result of external electromagnetic nois e. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by usin g pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral curren t consumption measured previously, the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the i/o supply voltage to supply the i/o pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: table 27. typical current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typ unit peripherals enabled peripherals disabled i dd supply current in run mode from v dd supply running from hse crystal clock 8 mhz, code executing from flash 48 mhz 23.5 13.5 ma 8 mhz 4.8 3.1 i dda supply current in run mode from v dda supply 48 mhz 163.3 163.3 a 8 mhz 2.5 2.5 i sw v ddiox f sw c = docid027114 rev 3 45/83 STM32F070CB/rb/c6/f6 electrical characteristics 69 where i sw is the current sunk by a switching i/ o to charge/discharge the capacitive load v ddiox is the i/o supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext + c s c s is the pcb board capacitance including the pad pin. the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. 6.3.6 wakeup time from low-power mode the wakeup times given in table 29 are the latency between the event and the execution of the first user instruction. the device goes in low-power mode after the wfe (wait for event) instruction, in the case of a wfi (wai t for interruption) inst ruction, 16 cpu cycles must be added to the following timings due to the interrupt latency in the cortex m0 architecture. the sysclk clock source setti ng is kept unchanged afte r wakeup from sleep mode. during wakeup from stop or standby mode, sysclk takes the default setting: hsi 8 mhz. the wakeup source from sleep and stop mode is an exti line configured in event mode. the wakeup source from standby mode is the wkup1 pin (pa0). all timings are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 20: general operating conditions . table 28. switching output i/o current consumption symbol parameter conditions (1) 1. c s = 7 pf (estimated value). i/o toggling frequency (f sw ) typ unit i sw i/o current consumption v ddiox = 3.3 v c ext = 0 pf c = c int + c ext + c s 4 mhz 0.18 ma 8 mhz 0.37 16 mhz 0.76 24 mhz 1.39 48 mhz 2.188 v ddiox = 3.3 v c ext = 22 pf c = c int + c ext + c s 4 mhz 0.49 8 mhz 0.94 16 mhz 2.38 24 mhz 3.99 v ddiox = 3.3 v c ext = 47 pf c = c int + c ext + c s c = c int 4 mhz 0.81 8 mhz 1.7 16 mhz 3.67 electrical characteristics STM32F070CB/rb/c6/f6 46/83 docid027114 rev 3 6.3.7 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillator is switched off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock inpu t waveform is shown in figure 11: high-speed external clock source ac timing diagram . figure 11. high-speed external cl ock source ac timing diagram table 29. low-power mode wakeup timings symbol parameter conditions typ @v dd = v dda max unit = 3.3 v t wustop wakeup from stop mode regulator in run mode 2.8 5 s t wustandby wakeup from standby mode - 51 - t wusleep wakeup from sleep mode - 4 sysclk cycles - table 30. high-speed external user clock characteristics symbol parameter (1) 1. guaranteed by design, not tested in production. min typ max unit f hse_ext user external clock source frequency - 8 32 mhz v hseh osc_in input pin high level voltage 0.7 v ddiox -v ddiox v v hsel osc_in input pin low level voltage v ss - 0.3 v ddiox t w(hseh) t w(hsel) osc_in high or low time 15 - - ns t r(hse) t f(hse) osc_in rise or fall time - - 20 0 6 9 9 + 6 ( + w i + 6 ( 7 + 6 ( w w u + 6 ( 9 + 6 ( / w z + 6 ( + w z + 6 ( / docid027114 rev 3 47/83 STM32F070CB/rb/c6/f6 electrical characteristics 69 low-speed external user clock generated from an external source in bypass mode the lse oscillator is switch ed off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock inpu t waveform is shown in figure 12 . figure 12. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 32 mhz crystal/ceramic resonator oscillator. all the information given in this pa ragraph are bas ed on design simulation results obtained with typical external components specified in table 32 . in the application, the resonator and the load capacito rs have to be placed as close as possible to the oscillator pins in order to minimize outpu t distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, pack age, accuracy). table 31. low-speed external user clock characteristics symbol parameter (1) 1. guaranteed by design, not tested in production. min typ max unit f lse_ext user external clock source frequency - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7 v ddiox -v ddiox v v lsel osc32_in input pin low level voltage v ss - 0.3 v ddiox t w(lseh) t w(lsel) osc32_in high or low time 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time - - 50 table 32. hse oscilla tor characteristics symbol parameter conditions (1) min (2) typ max (2) unit f osc_in oscillator frequency - 4 8 32 mhz r f feedback resistor - - 200 - k 0 6 9 9 / 6 ( + w i / 6 ( 7 / 6 ( w w u / 6 ( 9 / 6 ( / w z / 6 ( + w z / 6 ( / electrical characteristics STM32F070CB/rb/c6/f6 48/83 docid027114 rev 3 for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 20 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 13 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . figure 13. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal resonator oscillator. all the information gi ven in this paragraph are based on design simulation results i dd hse current consumption during startup (3) --8.5 ma v dd = 3.3 v, rm = 45 , cl = 10 pf@8 mhz -0.5- v dd = 3.3 v, rm = 30 , cl = 20 pf@32 mhz -1.5- g m oscillator transconductance startup 10 - - ma/v t su(hse) (4) startup time v dd is stabilized - 2 - ms 1. resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. guaranteed by design, not tested in production. 3. this consumption level occurs during the first 2/3 of the t su(hse) startup time 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonat or and it can vary significantly with the crystal manufacturer table 32. hse oscilla tor characteristics symbol parameter conditions (1) min (2) typ max (2) unit 0 6 9 2 6 & b , 1 2 6 & b 2 8 7 5 ) % l d v f r q w u r o o h g j d l q i + 6 ( 5 ( ; 7 0 + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v & / & / docid027114 rev 3 49/83 STM32F070CB/rb/c6/f6 electrical characteristics 69 obtained with typical external components specified in table 33 . in the application, the resonator and the load capa citors have to be placed as cl ose as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time . refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . figure 14. typical applicati on with a 32.768 khz crystal note: an external resistor is not required between osc32_in and osc32_out and it is forbidden to add one. table 33. lse oscillator characteristics (f lse = 32.768 khz) symbol parameter conditions (1) 1. refer to the note and caution paragraphs below the table, and to the applicat ion note an2867 ?oscillator design guide for st microcontrollers?. min (2) typ max (2) 2. guaranteed by design, not tested in production. unit i dd lse current consumption low drive capability - 0.5 0.9 a medium-low drive capability - - 1 medium-high drive capability - - 1.3 high drive capability - - 1.6 g m oscillator transconductance low drive capability 5 - - a/v medium-low drive capability 8 - - medium-high drive capability 15 - - high drive capability 25 - - t su(lse) (3) 3. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is meas ured for a standard crystal and it can vary significantly with the crystal manufacturer startup time v ddiox is stabilized - 2 - s 0 6 9 2 6 & b , 1 2 6 & b 2 8 7 ' u l y h s u r j u d p p d e o h d p s o l i l h u i / 6 ( n + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v & / & / electrical characteristics STM32F070CB/rb/c6/f6 50/83 docid027114 rev 3 6.3.8 internal clock source characteristics the parameters given in table 34 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 20: general operating conditions . the provided curves are characterization results, not tested in production. high-speed internal (hsi) rc oscillator high-speed internal 14 mhz (hsi14) rc oscillator (dedicated to adc) low-speed internal (lsi) rc oscillator table 34. hsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = -40 to 85c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - - 8 - mhz trim hsi user trimming step - - - 1 (2) 2. guaranteed by design, not tested in production. % ducy hsi duty cycle - 45 (2) -55 (2) % acc hsi accuracy of the hsi oscillator (factory calibrated) t a = -40 to 85c - 5 - % t a = 25c - 1 (3) 3. with user calibration. -% t su(hsi) hsi oscillator startup time - 1 (2) -2 (2) s i dda(hsi) hsi oscillator power consumption --80-a table 35. hsi14 oscillator characteristics (1) 1. v dda = 3.3 v, t a = -40 to 85 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi14 frequency - - 14 - mhz trim hsi14 user-trimming step - - - 1 (2) 2. guaranteed by design, not tested in production. % ducy (hsi14) duty cycle - 45 (2) -55 (2) % acc hsi14 accuracy of the hsi14 oscillator (factory calibrated) t a = ?40 to 85 c - 5 - % t su(hsi14) hsi14 oscillator startup time - 1 (2) -2 (2) s i dda(hsi14) hsi14 oscillator power consumption - - 100 - a table 36. lsi oscillator characteristics (1) symbol parameter min typ max unit f lsi frequency 30 40 50 khz docid027114 rev 3 51/83 STM32F070CB/rb/c6/f6 electrical characteristics 69 6.3.9 pll characteristics the parameters given in table 37 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 20: general operating conditions . 6.3.10 memory characteristics flash memory the characteristics are given at t a = -40 to 85 c unless otherwise specified. t su(lsi) (2) lsi oscillator startup time - - 85 s i dda(lsi) (2) lsi oscillator power consumption - 0.75 - a 1. v dda = 3.3 v, t a = -40 to 85 c unless otherwise specified. 2. guaranteed by design, not tested in production. table 36. lsi oscillator characteristics (1) symbol parameter min typ max unit table 37. pll characteristics symbol parameter value unit min typ max f pll_in pll input clock (1) 1. take care to use the appropriate multiplier factors to obtain pll input clock values compatible with the range defined by f pll_out . 1 (2) 8.0 24 (2) mhz pll input clock duty cycle 40 (2) -60 (2) % f pll_out pll multiplier output clock 16 (2) -48mhz t lock pll lock time - - 200 (2) 2. guaranteed by design, not tested in production. s jitter pll cycle-to-cycle jitter - - 300 (2) ps table 38. flash memory characteristics symbol parameter conditions min typ max (1) 1. guaranteed by design, not tested in production. unit t prog 16-bit programming time t a = -40 to +85 c - 53.5 - s t erase page erase time (2) 2. page size is 1kb for stm32f070x6 de vices and 2kb for stm32f070xb devices. t a = -40 to +85 c - 30 - ms t me mass erase time t a = -40 to +85 c - 30 - ms i dd supply current write mode - - 10 ma erase mode - - 12 ma v prog programming voltage - 2.4 - 3.6 v electrical characteristics STM32F070CB/rb/c6/f6 52/83 docid027114 rev 3 6.3.11 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a func tional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 40 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. software recommendations table 39. flash memory endurance and data retention symbol parameter conditions min (1) 1. data based on characterization results, not tested in production. unit n end endurance t a = -40 to +85 c 1 kcycle t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over the whole temperature range. 20 years table 40. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3v, lqfp48, t a = +25 c, f hclk = 48 mhz, conforming to iec 61000-4-2 3b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3v, lqfp48, t a = +25c, f hclk = 48 mhz, conforming to iec 61000-4-4 4b docid027114 rev 3 53/83 STM32F070CB/rb/c6/f6 electrical characteristics 69 the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o por ts). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. 6.3.12 electrical sens itivity characteristics based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. table 41. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/48 mhz s emi peak level v dd = 3.6 v, t a = 25 c, lqfp100 package compliant with iec 61967-2 0.1 to 30 mhz -3 dbv 30 to 130 mhz 23 130 mhz to 1 ghz 17 emi level 4 - electrical characteristics STM32F070CB/rb/c6/f6 54/83 docid027114 rev 3 static latch-up two complementary static te sts are required on six pa rts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin. ? a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with eia/jesd 78a ic latch-up standard. 6.3.13 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v ddiox (for standard, 3.3 v-capable i/o pins) should be avoided during normal product operation. however, in order to gi ve an indication of the robustness of the microcontroller in cases when abnormal injection a ccidentally happens, susceptibility tests are performed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (higher than 5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of the -5 a/+0 a range) or other functional failure (for example reset occurrence or oscillator freque ncy deviation). the characterization results are given in table 44 . negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. table 42. esd absolute maximum ratings symbol ratings conditions packages class maximum value (1) unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c, conforming to jesd22-a114 all 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c, conforming to ansi/esd stm5.3.1 all c4 500 v 1. data based on characterization results, not tested in production. table 43. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a docid027114 rev 3 55/83 STM32F070CB/rb/c6/f6 electrical characteristics 69 6.3.14 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 45 are derived from tests performed under the conditions summarized in table 20: general operating conditions . all i/os are designed as cmos- and ttl-compliant (except boot0). table 44. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 and pf1 pins -0 na ma injected current on pa9, pb3, pb13, pf11 pins with induced leakage current on adjacent pins less than 50 a -5 na injected current on pa11 and pa12 pins with induced leakage current on adjacent pins less than -1 ma -5 na injected current on all other ft and ftf pins -5 na injected current on pb0 and pb1 pins -5 na injected current on pc0 pin -0 +5 injected current on all other tta, tc and rst pins -5 +5 table 45. i/o static characteristics symbol parameter conditions min typ max unit v il low level input voltage tc and tta i/o - - 0.3 v ddiox +0.07 (1) v ft and ftf i/o - - 0.475 v ddiox ?0.2 (1) boot0 - - 0.3 v ddiox ?0.3 (1) all i/os except boot0 pin --0.3 v ddiox v ih high level input voltage tc and tta i/o 0.445 v ddiox +0.398 (1) -- v ft and ftf i/o 0.5 v ddiox +0.2 (1) -- boot0 0.2 v ddiox +0.95 (1) -- all i/os except boot0 pin 0.7 v ddiox -- v hys schmitt trigger hysteresis tc and tta i/o - 200 (1) - mv ft and ftf i/o - 100 (1) - boot0 - 300 (1) - electrical characteristics STM32F070CB/rb/c6/f6 56/83 docid027114 rev 3 all i/os are cmos- and ttl-compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 15 for standard i/os, and in figure 16 for 5 v tolerant i/os. the following curves are design simulation results, not tested in production. i lkg input leakage current (2) tc, ft and ftf i/o tta in digital mode v ss v in v ddiox -- 0.1 a tta in digital mode v ddiox v in v dda --1 tta in analog mode v ss v in v dda -- 0.2 ft and ftf i/o (3) v ddiox v in 5 v --10 r pu weak pull-up equivalent resistor (4) v in = v ss 25 40 55 k r pd weak pull-down equivalent resistor (4) v in = v ddiox 25 40 55 k c io i/o pin capacitance - - 5 - pf 1. data based on design simulation only. not tested in production. 2. the leakage could be higher than the maximum value, if negative current is injected on adjacent pins. refer to table 44: i/o current injection susceptibility . 3. to sustain a voltage higher than v ddiox + 0.3 v, the internal pull-up/pull- down resistors must be disabled. 4. pull-up and pull-down resistor s are designed with a true resistance in seri es with a switchable pmos/nmos. this pmos/nmos contribution to the series resistance is minimal (~10% order). table 45. i/o static characteristics (continued) symbol parameter conditions min typ max unit docid027114 rev 3 57/83 STM32F070CB/rb/c6/f6 electrical characteristics 69 figure 15. tc and tta i/o input characteristics figure 16. five volt tolerant (ft and ftf) i/o input characteristics 0 6 y 9 7 ( 6 7 ( ' 5 $ 1 * ( 7 ( 6 7 ( ' 5 $ 1 * ( 9 , + p l q 9 ' ' , 2 [ & 0 2 6 v w d q g d u g u h t x l u h p h q w 9 , / p d [ 9 ' ' , 2 [ & 0 2 6 v w d q g d u g u h t x l u h p h q w 8 1 ' ( ) , 1 ( ' , 1 3 8 7 5 $ 1 * ( 9 , + p l q 9 ' ' , 2 [ 9 , / p d [ 9 ' ' , 2 [ 9 , 1 9 9 ' ' , 2 [ 9 7 7 / v w d q g d u g u h t x l u h p h q w 7 7 / v w d q g d u g u h t x l u h p h q w 0 6 y 9 7 ( 6 7 ( ' 5 $ 1 * ( 7 ( 6 7 ( ' 5 $ 1 * ( 9 , + p l q 9 ' ' , 2 [ & 0 2 6 v w d q g d u g u h t x l u h p h q w 9 , / p d [ 9 ' ' , 2 [ & 0 2 6 v w d q g d u g u h t x l u h p h q w 8 1 ' ( ) , 1 ( ' , 1 3 8 7 5 $ 1 * ( 9 , + p l q 9 ' ' , 2 [ 9 , / p d [ 9 ' ' , 2 [ 9 , 1 9 9 ' ' , 2 [ 9 7 7 / v w d q g d u g u h t x l u h p h q w 7 7 / v w d q g d u g u h t x l u h p h q w electrical characteristics STM32F070CB/rb/c6/f6 58/83 docid027114 rev 3 output driving current the gpios (general purpose input/outputs) can sink or source up to +/-8 ma, and sink or source up to +/- 20 ma (with a relaxed v ol /v oh ). in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 6.2 : ? the sum of the currents sourced by all the i/os on v ddiox, plus the maximum consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see table 17: voltage characteristics ). ? the sum of the currents sunk by all the i/os on v ss , plus the maximu m consumption of the mcu sunk on v ss , cannot exceed the absolute maximum rating i vss (see table 17: voltage characteristics ). output voltage levels unless otherwise specified, th e parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 20: general operating conditions . all i/os are cmos- and ttl-compliant (ft, tta or tc unless otherwise specified). input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 17 and table 47 , respectively. unless otherwise specified, th e parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 20: general operating conditions . table 46. output voltage characteristics (1) symbol parameter conditions min max unit v ol output low level voltage for an i/o pin |i io | = 8 ma v ddiox 2.7 v -0.4 v v oh output high level voltage for an i/o pin v ddiox ?0.4 - v ol (2) output low level voltage for an i/o pin |i io | = 20 ma v ddiox 2.7 v -1.3 v v oh (2) output high level voltage for an i/o pin v ddiox ?1.3 - v ol (2) output low level voltage for an i/o pin |i io | = 6 ma -0.4 v v oh (2) output high level voltage for an i/o pin v ddiox ?0.4 - v olfm+ (2) output low level voltage for an ftf i/o pin in fm+ mode |i io | = 20 ma v ddiox 2.7 v -0.4v |i io | = 10 ma - 0.4 v 1. the i io current sourced or sunk by the device must alwa ys respect the absolute maxi mum rating specified in table 17: voltage characteristics , and the sum of the currents sourced or sunk by all the i/os (i/o ports and control pins) must always respect the absolute maximum ratings i io . 2. data based on characterization results. not tested in production. docid027114 rev 3 59/83 STM32F070CB/rb/c6/f6 electrical characteristics 69 table 47. i/o ac characteristics (1)(2) ospeedry [1:0] value (1) symbol parameter conditions min max unit x0 f max(io)out maximum frequency (3) c l = 50 pf, v ddiox 2.4 v -2mhz t f(io)out output fall time - 125 ns t r(io)out output rise time - 125 01 f max(io)out maximum frequency (3) c l = 50 pf, v ddiox 2.4 v -10mhz t f(io)out output fall time - 25 ns t r(io)out output rise time - 25 11 f max(io)out maximum frequency (3) c l = 30 pf, v ddiox 2.7 v - 50 mhz c l = 50 pf, v ddiox 2.7 v - 30 c l = 50 pf, 2.4 v v ddiox < 2.7 v - 20 t f(io)out output fall time c l = 30 pf, v ddiox 2.7 v - 5 ns c l = 50 pf, v ddiox 2.7 v - 8 c l = 50 pf, 2.4 v v ddiox < 2.7 v - 12 t r(io)out output rise time c l = 30 pf, v ddiox 2.7 v - 5 c l = 50 pf, v ddiox 2.7 v - 8 c l = 50 pf, 2.4 v v ddiox < 2.7 v - 12 fm+ configuration (4) f max(io)out maximum frequency (3) c l = 50 pf, v ddiox 2.4 v -2mhz t f(io)out output fall time - 12 ns t r(io)out output rise time - 34 -t extipw pulse width of external signals detected by the exti controller -10-ns 1. the i/o speed is configured using the ospeedrx[1:0] bits . refer to the stm32f0xxxx rm0360 reference manual for a description of gpio port configuration register. 2. guaranteed by design, not tested in production. 3. the maximum frequency is defined in figure 17 . 4. when fm+ configuration is set, the i/o speed control is bypassed. refer to the stm32f0xxxx reference manual rm0360 for a detailed description of fm+ i/o configuration. electrical characteristics STM32F070CB/rb/c6/f6 60/83 docid027114 rev 3 figure 17. i/o ac charac teristics definition 6.3.15 nrst pin characteristics the nrst pin input driver uses the cmos technology. it is connected to a permanent pull- up resistor, r pu . unless otherwise specified, th e parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 20: general operating conditions . 0 6 9 7 0 d [ l p x p i u h t x h q f \ l v d f k l h y h g l i w w ? z k h q o r d g h g e \ & v h h w k h w d e o h , 2 $ & f k d u d f w h u l v w l f v g h i l q l w l r q u i u , 2 r x w w i , 2 r x w w - 7 d q g l i w k h g x w \ f \ f o h l v table 48. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) nrst input low level voltage - - - 0.3 v dd +0.07 (1) v v ih(nrst) nrst input high level voltage - 0.445 v dd +0.398 (1) -- v hys(nrst) nrst schmitt trigger voltage hysteresis --200-mv r pu weak pull-up equivalent resistor (2) v in = v ss 25 40 55 k v f(nrst) nrst input filtered pulse - - - 100 (1) ns v nf(nrst) nrst input not filtered pulse 2.7 < v dd < 3.6 300 (3) -- ns 2.4 < v dd < 3.6 500 (3) -- 1. data based on design simulation only. not tested in production. 2. the pull-up is designed with a true re sistance in series with a switchable pmos . this pmos contribution to the series resistance is minimal (~10% order). 3. data based on design simulation only. not tested in production. docid027114 rev 3 61/83 STM32F070CB/rb/c6/f6 electrical characteristics 69 figure 18. recommended nrst pin protection 1. the external capacitor protects the device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 48: nrst pin characteristics . otherwise the reset will not be taken into account by the device. 6.3.16 12-bit adc characteristics unless otherwise specified, the parameters given in table 49 are preliminary values derived from tests performed under ambient temperature, f pclk frequency and v dda supply voltage conditions su mmarized in table 20: general operating conditions . note: it is recommended to perform a calibration after each power-up. 0 6 9 5 3 8 9 ' ' , q w h u q d o u h v h w ( [ w h u q d o u h v h w f l u f x l w 1 5 6 7 ) l o w h u ? ) table 49. adc characteristics symbol parameter conditions min typ max unit v dda analog supply voltage for adc on - 2.4 - 3.6 v i dda (adc) current consumption of the adc (1) v dd = v dda = 3.3 v - 0.9 - ma f adc adc clock frequency - 0.6 - 14 mhz f s (2) sampling rate - 0.05 - 1 mhz f trig (2) external trigger frequency f adc = 14 mhz - - 823 khz ---171/f adc v ain conversion voltage range - 0 - v dda v r ain (2) external input impedance see equation 1 and table 50 for details --50k r adc (2) sampling switch resistance ---1k c adc (2) internal sample and hold capacitor ---8pf electrical characteristics STM32F070CB/rb/c6/f6 62/83 docid027114 rev 3 equation 1: r ain max formula the formula above ( equation 1 ) is used to dete rmine the maximum external impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). t cal (2)(3) calibration time f adc = 14 mhz 5.9 s -831/f adc w latency (2)(4) adc_dr register write latency adc clock = hsi14 1.5 adc cycles + 2 f pclk cycles - 1.5 adc cycles + 3 f pclk cycles - adc clock = pclk/2 - 4.5 - f pclk cycle adc clock = pclk/4 - 8.5 - f pclk cycle t latr (2) trigger conversion latency f adc = f pclk /2 = 14 mhz 0.196 s f adc = f pclk /2 5.5 1/f pclk f adc = f pclk /4 = 12 mhz 0.219 s f adc = f pclk /4 10.5 1/f pclk f adc = f hsi14 = 14 mhz 0.188 - 0.259 s jitter adc adc jitter on trigger conversion f adc = f hsi14 -1-1/f hsi14 t s (2) sampling time f adc = 14 mhz 0.107 - 17.1 s - 1.5 - 239.5 1/f adc t stab (2) stabilization time - 14 1/f adc t conv (2) total conversion time (including sampling time) f adc = 14 mhz, 12-bit resolution 1 - 18 s 12-bit resolution 14 to 252 (t s for sampling +12.5 for successive approximation) 1/f adc 1. during conversion of the sampled value (12.5 x adc cl ock period), an additional consumption of 100 a on i dda and 60 a on i dd should be taken into account. 2. guaranteed by design, not tested in production. 3. specified value includes only adc timing. it does not include the latency of the register access. 4. this parameter specify latency for transfer of the conversion result to the adc_dr register. eoc flag is set at this time. table 49. adc characteristics (continued) symbol parameter conditions min typ max unit r ain t s f adc c adc 2 n2 + () ln --------------------------------------------------------------- - r adc ? < docid027114 rev 3 63/83 STM32F070CB/rb/c6/f6 electrical characteristics 69 table 50. r ain max for f adc = 14 mhz t s (cycles) t s (s) r ain max (k ) (1) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.52.0425.2 41.52.9637.2 55.5 3.96 50 71.5 5.11 na 239.5 17.1 na 1. guaranteed by design, not tested in production. table 51. adc accuracy (1)(2)(3) symbol parameter test conditions typ max (4) unit et total unadjusted error f pclk = 48 mhz, f adc = 14 mhz, r ain < 10 k v dda = 2.7 v to 3.6 v t a = ? 40 to 85 c 3.3 4 lsb eo offset error 1.9 2.8 eg gain error 2.8 3 ed differential linearity error 0.7 1.3 el integral linearity error 1.2 1.7 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negativ e current on any of the standard (non-robust) analog input pins should be avoided as this signific antly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to gr ound) to standard analog pins which may potentially inject negative current. any positive injection current wi thin the limits specified for i inj(pin) and i inj(pin) in section 6.3.14 does not affect the adc accuracy. 3. better performance may be achieved in restricted v dda , frequency and temperature ranges. 4. data based on characterization re sults, not tested in production. electrical characteristics STM32F070CB/rb/c6/f6 64/83 docid027114 rev 3 figure 19. adc accuracy characteristics figure 20. typical connecti on diagram using the adc 1. refer to table 49: adc characteristics for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 9: power supply scheme . the 10 nf capacitor should be ceramic (good qualit y) and it should be placed as close as possible to the chip. ( 7 7 r w d o 8 q d m x v w h g ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q w k h d f w x d o d q g l g h d o w u d q v i h u f x u y h v ( 2 2 i i v h w ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q w k h i l u v w d f w x d o w u d q v l w l r q d q g w k h i l u v w l g h d o r q h ( * * d l q ( u u r u g h y l d w l r q e h w z h h q w k h o d v w l g h d o w u d q v l w l r q d q g w k h o d v w d f w x d o r q h ( ' ' l i i h u h q w l d o / l q h d u l w \ ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q d f w x d o v w h s v d q g w k h l g h d o r q h v ( / , q w h j u d o / l q h d u l w \ ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q d q \ d f w x d o w u d q v l w l r q d q g w k h h q g s r l q w f r u u h o d w l r q o l q h ( [ d p s o h r i d q d f w x d o w u d q v i h u f x u y h 7 k h l g h d o w u d q v i h u f x u y h ( q g s r l q w f r u u h o d w l r q o l q h 9 ' ' $ 9 6 6 $ ( 2 ( 7 ( / ( * ( ' / 6 % , ' ( $ / 0 6 9 0 6 9 9 ' ' $ $ , 1 [ , / ? ? $ 9 7 5 $ , 1 & s d u d v l w l f 9 $ , 1 9 7 5 $ ' & e l w f r q y h u w h u & $ ' & 6 d p s o h d q g k r o g $ ' & f r q y h u w h u docid027114 rev 3 65/83 STM32F070CB/rb/c6/f6 electrical characteristics 69 6.3.17 temperature sensor characteristics 6.3.18 timer characteristics the parameters given in the followi ng tables are guaranteed by design. refer to section 6.3.14: i/o port characteristics for details on the input/output alternate function characteristics (output compare, i nput capture, external clock, pwm output). table 52. ts characteristics symbol parameter min typ max unit t l (1) v sense linearity with temperature - 1 2c avg_slope (1) average slope 4.0 4.3 4.6 mv/c v 30 voltage at 30 c ( 5 c) (2) 1.34 1.43 1.52 v t start (1) adc_in16 buffer startup time - - 10 s t s_temp (1) adc sampling time when reading the temperature 4- -s 1. guaranteed by design, not tested in production. 2. measured at v dda = 3.3 v 10 mv. the v 30 adc conversion result is stored in the ts_cal1 byte . refer to table 2: temperature sensor calibration values . table 53. timx characteristics symbol parameter conditions min typ max unit t res(tim) timer resolution --1- t timxclk f timxclk = 48 mhz - 20.8 - ns f ext timer external clock frequency on ch1 to ch4 -- f timxclk /2 -mhz f timxclk = 48 mhz - 24 - mhz t max_count 16-bit timer maximum period -- 2 16 - t timxclk f timxclk = 48 mhz - 1365 - s 32-bit timer maximum period -- 2 32 - t timxclk f timxclk = 48 mhz - 89.48 - s electrical characteristics STM32F070CB/rb/c6/f6 66/83 docid027114 rev 3 6.3.19 communication interfaces i 2 c interface characteristics the i2c interface meets the timings requirements of the i 2 c-bus specification and user manual rev. 03 for: ? standard-mode (sm): with a bit rate up to 100 kbit/s ? fast-mode (fm): with a bit rate up to 400 kbit/s ? fast-mode plus (fm+): with a bit rate up to 1 mbit/s. the i2c timings requirements are guaranteed by design when the i2c peripheral is properly configured (refer to reference manual). the sda and scl i/o requirements are met with the following restrictions: the sda and scl i/o pins are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v ddiox is disabled, but is still present. only ftf i/o pins support fm+ low level output current maximum requirement. refer to section 6.3.14: i/o port characteristics for the i2c i/os characteristics. all i2c sda and scl i/os embed an analog filter. refer to the table below for the analog filter characteristics: table 54. iwdg min/max timeout period at 40 khz (lsi) (1) 1. these timings are given for a 40 kh z clock but the microcontroller inte rnal rc frequency can vary from 30 to 60 khz. moreover, given an ex act rc oscillator frequency, the ex act timings still depend on the phasing of the apb interface clock versus the lsi clock so t hat there is always a full rc period of uncertainty. prescaler divider pr[2:0] bits min timeout rl[11:0]= 0x000 max timeout rl[11:0]= 0xfff unit /4 0 0.1 409.6 ms /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 6 or 7 6.4 26214.4 table 55. wwdg min/max timeout value at 48 mhz (pclk) prescaler wdgtb min timeout value max timeout value unit 1 0 0.0853 5.4613 ms 2 1 0.1706 10.9226 4 2 0.3413 21.8453 8 3 0.6826 43.6906 docid027114 rev 3 67/83 STM32F070CB/rb/c6/f6 electrical characteristics 69 spi characteristics unless otherwise specified, the parameters given in table 57 for spi are derived from tests performed under the ambient temperature, f pclkx frequency and supply voltage conditions summarized in table 20: general operating conditions . refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics. table 56. i2c analog filter characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter min max unit t af maximum pulse width of spikes that are suppressed by the analog filter 50 (2) 2. spikes with widths below t af(min) are filtered. 260 (3) 3. spikes with widths above t af(max) are not filtered ns table 57. spi characteristics (1) symbol parameter con ditions min max unit f sck 1/t c(sck) spi clock frequency master mode - 18 mhz slave mode - 18 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 15 pf - 6 ns t su(nss) nss setup time slave mode 4tpclk - ns t h(nss) nss hold time slave mode 2tpclk + 10 - t w(sckh) t w(sckl) sck high and low time master mode, f pclk = 36 mhz, presc = 4 tpclk/2 -2 tpclk/2 + 1 t su(mi) t su(si) data input setup time master mode 4 - slave mode 5 - t h(mi) data input hold time master mode 4 - t h(si) slave mode 5 - t a(so) (2) data output access time slave mode, f pclk = 20 mhz 0 3tpclk t dis(so) (3) data output disable time slave mode 0 18 t v(so) data output valid time slave mode (after enable edge) - 22.5 t v(mo) data output valid time master mode (after enable edge) - 6 t h(so) data output hold time slave mode (after enable edge) 11.5 - t h(mo) master mode (after enable edge) 2 - ducy(sck) spi slave input clock duty cycle slave mode 25 75 % 1. data based on characterization results, not tested in production. 2. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. min time is for the minimum time to invalidate the output and th e max time is for the maximum time to put the data in hi-z electrical characteristics STM32F070CB/rb/c6/f6 68/83 docid027114 rev 3 figure 21. spi timing diagram - slave mode and cpha = 0 figure 22. spi timing diagram - slave mode and cpha = 1 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . d l f 6 & . , q s x w 1 6 6 l q s x w w 6 8 1 6 6 w f 6 & . w k 1 6 6 & 3 + $ & 3 2 / & 3 + $ & 3 2 / w z 6 & . + w z 6 & . / w 9 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 w d 6 2 0 , 6 2 2 8 7 3 8 7 0 2 6 , , 1 3 8 7 0 6 % 2 8 7 % , 7 2 8 7 / 6 % 2 8 7 w v x 6 , w k 6 , 0 6 % , 1 % , 7 , 1 / 6 % , 1 d l e 1 6 6 l q s x w w 6 8 1 6 6 w f 6 & . w k 1 6 6 6 & . l q s x w & 3 + $ & 3 2 / & 3 + $ & 3 2 / w z 6 & . + w z 6 & . / w d 6 2 w y 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 0 , 6 2 2 8 7 3 8 7 0 2 6 , , 1 3 8 7 w v x 6 , w k 6 , 0 6 % 2 8 7 0 6 % , 1 % , 7 2 8 7 / 6 % 2 8 7 / 6 % , 1 % , 7 , 1 docid027114 rev 3 69/83 STM32F070CB/rb/c6/f6 electrical characteristics 69 figure 23. spi timing diagram - master mode 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . usb characteristics the STM32F070CB/rb/c6/f6 usb interface is fully compliant with the usb specification version 2.0 and is usb-if certifie d (for full-speed device operation). d l f 6 & . 2 x w s x w & 3 + $ 0 2 6 , 2 8 7 3 8 7 0 , 6 2 , 1 3 8 7 & 3 + $ / 6 % 2 8 7 / 6 % , 1 & 3 2 / & 3 2 / % , 7 2 8 7 1 6 6 l q s x w w f 6 & . w z 6 & . + w z 6 & . / w u 6 & . w i 6 & . w k 0 , + l j k 6 & . 2 x w s x w & 3 + $ & 3 + $ & 3 2 / & 3 2 / w v x 0 , w y 0 2 w k 0 2 0 6 % , 1 % , 7 , 1 0 6 % 2 8 7 table 58. usb electrical characteristics symbol parameter condi tions min. typ max. unit v dd usb transceiver operating voltage -3.0 (1) 1. the STM32F070CB/rb/c6/f6 usb functionality is ens ured down to 2.7 v, but the usb electrical characteristics are degraded in the 2.7-to-3.0 v voltage range. -3.6v t startup (2) 2. guaranteed by design, not tested in production. usb transceiver startup time - - - 1.0 s r pui embedded usb_dp pull-up value during idle - 1.1 1.26 1.5 k r pur embedded usb_dp pull-up value during reception - 2.0 2.26 2.6 z drv (2) output driver impedance (3) 3. no external termination series resistors are requi red on usb_dp (d+) and usb_dm (d-); the matching impedance is already included in the embedded driver. driving high and low 28 40 44 package information STM32F070CB/rb/c6/f6 70/83 docid027114 rev 3 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 7.1 lqfp64 package information lqfp64 is 64-pin, 10 x 10 mm low-profile quad flat package. figure 24. lqfp64 outline 1. drawing is not to scale. table 59. lqfp64 mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 : b 0 ( b 9 $ $ $ 6 ( $ 7 , 1 * 3 / $ 1 ( f f f & e & f $ / / . , ' ( 1 7 , ) , & $ 7 , 2 1 3 , 1 ' ' ' h ( ( ( * $ 8 * ( 3 / $ 1 ( p p docid027114 rev 3 71/83 STM32F070CB/rb/c6/f6 package information 80 figure 25. lqfp64 recommended footprint 1. dimensions are expr essed in millimeters. b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d - 12.000 - - 0.4724 - d1 - 10.000 - - 0.3937 - d3 - 7.500 - - 0.2953 - e - 12.000 - - 0.4724 - e1 - 10.000 - - 0.3937 - e3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - k 03.57 03.57 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 59. lqfp64 mechanical data (continued) symbol millimeters inches (1) min typ max min typ max a i c package information STM32F070CB/rb/c6/f6 72/83 docid027114 rev 3 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 26. lqfp64 marking example (package top view) 1. parts marked as "es", "e" or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 3 u r g x f w l g h q w l i l f d w l r q 3 l q l g h q w l i l f d w l r q ' d w h f r g h 5 h y l v l r q f r g h : 8 8 4 5 . ' 3 # 5 3 0 6 9 docid027114 rev 3 73/83 STM32F070CB/rb/c6/f6 package information 80 7.2 lqfp48 package information lqfp48 is a 48-pin, 7 x 7 mm low-profile quad flat package figure 27. lqfp48 outline 1. drawing is not to scale. table 60. lqfp48 mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.500 - - 0.2165 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 " ? - % ? 6 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . c c c # # $ m m ' ! 5 ' % 0 , ! . % b ! ! ! c ! , , $ $ % % % e 3 % ! 4 ) . ' 0 , ! . % + package information STM32F070CB/rb/c6/f6 74/83 docid027114 rev 3 figure 28. lqfp48 recommended footprint 1. dimensions are expr essed in millimeters. e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 60. lqfp48 mechanical data (continued) symbol millimeters inches (1) min typ max min typ max a i d docid027114 rev 3 75/83 STM32F070CB/rb/c6/f6 package information 80 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 29. lqfp48 marking example (package top view) 1. parts marked as "es", "e" or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 9 3 l q l g h q w l i l f d w l r q ' h y l f h l g h q w l i l f d w l r q 4 5 . ' $ # 5 3 : 8 8 ' d w h f r g h 5 h y l v l r q f r g h package information STM32F070CB/rb/c6/f6 76/83 docid027114 rev 3 7.3 tssop20 package information tssop20 is a 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch package. figure 30.tsso p20 outline 1. drawing is not to scale. table 61. tssop20 mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a - - 1.200 - - 0.0472 a1 0.050 - 0.150 0.0020 - 0.0059 a2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 c 0.090 - 0.200 0.0035 - 0.0079 d 6.400 6.500 6.600 0.2520 0.2559 0.2598 e 6.200 6.400 6.600 0.2441 0.2520 0.2598 e1 4.300 4.400 4.500 0.1693 0.1732 0.1772 e - 0.650 - - 0.0256 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - z z d z s? ? > ? l > ^ d / e ' w > e ' h ' w > e x?? uu w / e / e d / & / d / k e docid027114 rev 3 77/83 STM32F070CB/rb/c6/f6 package information 80 figure 31. tssop20 footprint 1. dimensions are expr essed in millimeters. k 0 - 8 0 - 8 aaa - - 0.100 - - 0.0039 1. values in inches are converted fr om mm and rounded to four decimal digits. table 61. tssop20 mechanical data (continued) symbol millimeters inches (1) min. typ. max. min. typ. max. 9 ! ? & 0 ? 6 package information STM32F070CB/rb/c6/f6 78/83 docid027114 rev 3 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 32. tssop20 marking example (package top view) 1. parts marked as "es", "e" or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 9 5 h y l v l r q f r g h ' d w h f r g h ' h y l f h l g h q w l i l f d w l r q 3 l q l g h q w l i l f d w l r q ' ' 1 : 8 8 3 docid027114 rev 3 79/83 STM32F070CB/rb/c6/f6 package information 80 7.4 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 20: general operating conditions . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd - v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 7.4.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org table 62. package thermal characteristics symbol parameter value unit j thermal resistance junction-ambient lqfp64 - 10 mm x 10 mm 44 c/w thermal resistance junction-ambient lqfp48 - 7 mm x 7 mm 55 thermal resistance junction-ambient tssop20 - 6.5 mm x 6.4 mm 76 ordering information STM32F070CB/rb/c6/f6 80/83 docid027114 rev 3 8 ordering information for a list of available options (memory, package, and so on) or for further information on any aspect of this device, please cont act your nearest st sales office. + table 63. ordering information scheme example : stm32 f 070 c 6 t 6 x device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose sub-family 070 = stm32f070xx pin count f = 20 pins c = 48 pins r = 64 pins code size 6 = 32 kbyte of flash memory b = 128 kbyte of flash memory package p = tssop t = lqfp temperature range 6 = ?40 to 85 c options xxx = programmed parts tr = tape and reel docid027114 rev 3 81/83 STM32F070CB/rb/c6/ f6 revision history 82 9 revision history table 64. document revision history date revision changes 27-nov-2014 1 initial release. 15-jan-2015 2 updated the number of spi in features and section: description . updated section: serial peripheral interface (spi). updated the fourth footnote of table: stm32f070xb/i pin definitions , and added the reference to pb9 pin. moved the af3 data to af4 for pa9 and pa10 pins in table: alternate functions selected through gpioa_afr registers for port a . added the reference to footnote 1 to af0 data for pb12, pb13, pb14 and pb15, and to af5 data for pb9 and pb10 in table: alternate functions selected through gpiob_afr registers for port b . added the reference to footnote 1 to spi2 in table: stm32f070xb/6 peripheral register boundary addressesf070. 07-feb-2016 3 updated: ? removal of table 1 from cover page (all part numbers put in the header) ? table 1: STM32F070CB/rb/c6/f6 family device features and peripheral counts ; number of int. adc channels corrected ? figure 1: block diagram ? figure 2: clock tree ? table 7: stm32f70x0 usart implementation ? figure 6: STM32F070CB/ rb/c6/f6 memory map and added the note related to the start address of the system memory ? figure 9: power supply scheme ? section 3.5.1: power supply schemes ? section 3.11: timers and watchdogs - number of complementary outputs in the table ? table 10: stm32f070xb/6 pin definitions - tssop20 pinout correction, pins 10, 15 and 16 ? table 23: embedded internal reference voltage : added t start , changed v refint and t s_vrefint values and notes ? table 33: lse oscillator characteristics (f lse = 32.768 khz) lsedrv[1:0] values removed (see ref. manual) ? table 49: adc characteristics - t stab defined relative to clock frequency; notes 3. and 4. added ? table 52: ts characteristics : removed the min. value for t start revision history stm 32f070cb/rb/c6/f6 82/83 docid027114 rev 3 07-feb-2016 3 ? figure 15 and figure 16 improved ? section 7: package information name and structure change ? section 8: ordering information renamed from part numbering; removed undue code sizes table 64. document revision history (continued) date revision changes docid027114 rev 3 83/83 STM32F070CB/rb/c6/f6 83 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 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